Merge #88

88: make compilable on stable r=japaric a=japaric

This PR makes this crate compilable on stable when the "inline-asm" and "singleton" Cargo features
are disabled (they are enabled by default to maintain backwards compatibility).

The main change has been replacing almost (\*) all inline `asm!` invocations with FFI calls into
external assembly files.

(\*) Stuff that has not been converted into external assembly file and thus is not available on
stable:

- Reading the (A)PSR register (I'm not sure if this will work with the extra function call overhead)

- Reading and writing the Link Register (LR)

- Reading and writing the Program Counter (PC)

I would appreciate if someone checked that all the stuff that's now using FFI calls has the same
semantics as the inline `asm!` version.


Co-authored-by: Jorge Aparicio <jorge@japaric.io>

.travis.yml

@@ -3,15 +3,62 @@ language: rust
 matrix:
   include:
     - env: TARGET=x86_64-unknown-linux-gnu
-      rust: nightly
+
+    - env: TARGET=thumbv6m-none-eabi
+      rust: beta
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+    - env: TARGET=thumbv7m-none-eabi
+      rust: beta
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+    - env: TARGET=thumbv7em-none-eabi
+      rust: beta
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
+    - env: TARGET=thumbv7em-none-eabihf
+      rust: beta
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
     - env: TARGET=thumbv6m-none-eabi
       rust: nightly
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
     - env: TARGET=thumbv7m-none-eabi
       rust: nightly
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
     - env: TARGET=thumbv7em-none-eabi
       rust: nightly
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
+
     - env: TARGET=thumbv7em-none-eabihf
       rust: nightly
+      addons:
+        apt:
+          packages:
+            - gcc-arm-none-eabi
 
 before_install: set -e
 

CHANGELOG.md

@@ -5,7 +5,47 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/)
 and this project adheres to [Semantic Versioning](http://semver.org/).
 
-## [Unreleased]
+## [v0.5.0] - 2018-05-11
+
+### Added
+
+- `DebugMonitor` and `SecureFault` variants to the `Exception` enumeration.
+
+- An optional `"inline-asm"` feature
+
+### Changed
+
+- [breaking-change] This crate now requires `arm-none-eabi-gcc` to be installed and available in
+  `$PATH` when built with the `"inline-asm"` feature disabled (which is disabled by default).
+
+- [breaking-change] The `register::{apsr,lr,pc}` modules are now behind the `"inline-asm"` feature.
+
+- [breaking-change] Some variants of the `Exception` enumeration are no longer available on
+  `thumbv6m-none-eabi`. See API docs for details.
+
+- [breaking-change] fixed typo in `shcrs` field of `scb::RegisterBlock`; it was previously named
+  `shpcrs`.
+
+- [breaking-change] removed several fields from `scb::RegisterBlock` on ARMv6-M. These registers are
+  not available on that sub-architecture.
+
+- [breaking-change] changed the type of `scb::RegisterBlock.shpr` from `RW<u8>` to `RW<u32>` on
+  ARMv6-M. These registers are word accessible only on that sub-architecture.
+
+- [breaking-change] renamed the `mmar` field of `scb::RegisterBlock` to `mmfar` to match the CMSIS
+  name.
+
+- [breaking-change] removed the `iabr` field from `scb::RegisterBlock` on ARMv6-M. This register is
+  not available on that sub-architecture.
+
+- [breaking-change] removed several fields from `cpuid::RegisterBlock` on ARMv6-M. These registers
+  are not available on that sub-architecture.
+
+### Removed
+
+- [breaking-change] The `exception` module has been removed. A replacement for `Exception::active`
+  can be found in `SCB::vect_active`. A modified version `exception::Exception` can be found in the
+  `peripheral::scb` module.
 
 ## [v0.4.3] - 2018-01-25
 

Cargo.toml

@@ -7,13 +7,16 @@ keywords = ["arm", "cortex-m", "register", "peripheral"]
 license = "MIT OR Apache-2.0"
 name = "cortex-m"
 repository = "https://github.com/japaric/cortex-m"
-version = "0.4.3"
+version = "0.5.0"
+
+[build-dependencies]
+cc = "1.0.10"
 
 [dependencies]
-aligned = "0.1.1"
-bare-metal = "0.1.0"
+aligned = "0.2.0"
+bare-metal = "0.2.0"
 volatile-register = "0.2.0"
-untagged-option = "0.1.1"
 
 [features]
 cm7-r0p1 = []
+inline-asm = []

asm/basepri_max-cm7-r0p1.s

@@ -0,0 +1,11 @@
+  .global __basepri_max
+  .syntax unified
+__basepri_max:
+  mrs r1, PRIMASK
+  cpsid i
+  tst.w r1, #1
+  msr BASEPRI_MAX, r0
+  it ne
+  bxne lr
+  cpsie i
+  bx lr

asm/basepri_max.s

@@ -0,0 +1,4 @@
+  .global __basepri_max
+__basepri_max:
+  msr BASEPRI_MAX, r0
+  bx lr

asm/basepri_r.s

@@ -0,0 +1,4 @@
+  .global __basepri_r
+__basepri_r:
+  mrs r0, BASEPRI
+  bx lr

asm/basepri_w-cm7-r0p1.s

@@ -0,0 +1,11 @@
+  .global __basepri_w
+  .syntax unified
+__basepri_w:
+  mrs r1, PRIMASK
+  cpsid i
+  tst.w r1, #1
+  msr BASEPRI, r0
+  it ne
+  bxne lr
+  cpsie i
+  bx lr

asm/basepri_w.s

@@ -0,0 +1,4 @@
+  .global __basepri_w
+__basepri_w:
+  msr BASEPRI, r0
+  bx lr

asm/bkpt.s

@@ -0,0 +1,4 @@
+  .global __bkpt
+__bkpt:
+  bkpt
+  bx lr

asm/control.s

@@ -0,0 +1,4 @@
+  .global __control
+__control:
+  mrs r0, CONTROL
+  bx lr

asm/cpsid.s

@@ -0,0 +1,4 @@
+  .global __cpsid
+__cpsid:
+  cpsid i
+  bx lr

asm/cpsie.s

@@ -0,0 +1,4 @@
+  .global __cpsie
+__cpsie:
+  cpsie i
+  bx lr

asm/dmb.s

@@ -0,0 +1,4 @@
+  .global __dmb
+__dmb:
+  dmb 0xF
+  bx lr

asm/dsb.s

@@ -0,0 +1,4 @@
+  .global __dsb
+__dsb:
+  dsb 0xF
+  bx lr

asm/faultmask.s

@@ -0,0 +1,4 @@
+  .global __faultmask
+__faultmask:
+  mrs r0, FAULTMASK
+  bx lr

asm/isb.s

@@ -0,0 +1,4 @@
+  .global __isb
+__isb:
+  isb 0xF
+  bx lr

asm/msp_r.s

@@ -0,0 +1,4 @@
+  .global __msp_r
+__msp_r:
+  mrs r0, MSP
+  bx lr

asm/msp_w.s

@@ -0,0 +1,4 @@
+  .global __msp_w
+__msp_w:
+  msr MSP, r0
+  bx lr

asm/nop.s

@@ -0,0 +1,3 @@
+  .global __nop
+__nop:
+  bx lr

asm/primask.s

@@ -0,0 +1,4 @@
+  .global __primask
+__primask:
+  mrs r0, PRIMASK
+  bx lr

asm/psp_r.s

@@ -0,0 +1,4 @@
+  .global __psp_r
+__psp_r:
+  mrs r0, PSP
+  bx lr

asm/psp_w.s

@@ -0,0 +1,4 @@
+  .global __psp_w
+__psp_w:
+  msr PSP, r0
+  bx lr

asm/sev.s

@@ -0,0 +1,4 @@
+  .global __sev
+__sev:
+  sev
+  bx lr

asm/wfe.s

@@ -0,0 +1,4 @@
+  .global __wfe
+__wfe:
+  wfe
+  bx lr

asm/wfi.s

@@ -0,0 +1,4 @@
+  .global __wfi
+__wfi:
+  wfi
+  bx lr

build.rs

@@ -1,18 +1,58 @@
+extern crate cc;
+
 use std::env;
 
 fn main() {
     let target = env::var("TARGET").unwrap();
 
+    if target.starts_with("thumb") && env::var_os("CARGO_FEATURE_INLINE_ASM").is_none() {
+        // NOTE we need to place each routine in a separate assembly file or the linker won't be
+        // able to discard the unused routines
+        let mut build = cc::Build::new();
+        build
+            .file("asm/basepri_r.s")
+            .file("asm/bkpt.s")
+            .file("asm/control.s")
+            .file("asm/cpsid.s")
+            .file("asm/cpsie.s")
+            .file("asm/dmb.s")
+            .file("asm/dsb.s")
+            .file("asm/faultmask.s")
+            .file("asm/isb.s")
+            .file("asm/msp_r.s")
+            .file("asm/msp_w.s")
+            .file("asm/nop.s")
+            .file("asm/primask.s")
+            .file("asm/psp_r.s")
+            .file("asm/psp_w.s")
+            .file("asm/sev.s")
+            .file("asm/wfe.s")
+            .file("asm/wfi.s");
+
+        if env::var_os("CARGO_FEATURE_CM7_R0P1").is_some() {
+            build.file("asm/basepri_max-cm7-r0p1.s");
+            build.file("asm/basepri_w-cm7-r0p1.s");
+        } else {
+            build.file("asm/basepri_max.s");
+            build.file("asm/basepri_w.s");
+        }
+
+        build.compile("asm");
+    }
+
     if target.starts_with("thumbv6m-") {
+        println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv6m");
     } else if target.starts_with("thumbv7m-") {
+        println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv7m");
     } else if target.starts_with("thumbv7em-") {
+        println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv7m");
         //println!("cargo:rustc-cfg=armv7em");
     }
 
-    if target.ends_with("eabihf") {
+    if target.ends_with("-eabihf") {
         println!("cargo:rustc-cfg=has_fpu");
     }
 }

ci/script.sh

@@ -1,15 +1,25 @@
 set -euxo pipefail
 
 main() {
+    cargo check --target $TARGET
+
+    if [ $TRAVIS_RUST_VERSION = nightly ]; then
+        cargo check --target $TARGET --features inline-asm
+    fi
+
     case $TARGET in
         thumbv7em-none-eabi*)
             cargo check --target $TARGET --features cm7-r0p1
-            cargo check --target $TARGET
+
+            if [ $TRAVIS_RUST_VERSION = nightly ]; then
+                cargo check --target $TARGET --features 'cm7-r0p1 inline-asm'
+            fi
             ;;
+
         thumbv*-none-eabi*)
-            cargo check --target $TARGET
             ;;
-        *)
+
+        x86_64-unknown-linux-gnu)
             cargo test --target $TARGET
             ;;
     esac