Version 23.1.0.0

gem5 Version 23.1 is our first release where the development has been on GitHub.
During this release, there have been 362 pull requests merged which comprise 416 commits with 51 unique contributors.

Significant API and user-facing changes

The gem5 build can is now configured with kconfig

• Most gem5 builds without customized options (excluding double dash options) (e.g. , build/X86/gem5.opt) are backwards compatible and require no changes to your current workflows.
• All of the default builds in build_opts are unchanged and still available.
• However, if you want to specialize your build. For example, use customized ruby protocol. The command scons PROTOCOL=<PROTOCAL_NAME> build/ALL/gem5.opt will not work anymore. you now have to use scons <kconfig command> to update the ruby protocol as example. The double dash options (--without-tcmalloc, --with-asan and so on) are still continue to work as normal.
• For more details refer to the documentation here: kconfig documentation

Standard library improvements

WorkloadResource added to resource specialization

• The Workload and CustomWorkload classes are now deprecated. They have been transformed into wrappers for the obtain_resource and WorkloadResource classes in resource.py, respectively.
• Code utilizing the older API will continue to function as expected but will trigger a warning message. To update code using the Workload class, change the call from Workload(id='resource_id', resource_version='1.0.0') to obtain_resource(id='resource_id', resource_version='1.0.0'). Similarly, to update code using the CustomWorkload class, change the call from CustomWorkload(function=func, parameters=params) to WorkloadResource(function=func, parameters=params).
• Workload resources in gem5 can now be directly acquired using the obtain_resource function, just like other resources.

Introducing Suites

Suites is a new category of resource being introduced in gem5. Documentation of suites can be found here: suite documentation.

Other API changes

• All resource object now have their own id and category. Each resource class has its own __str__() function which return its information in the form of category(id, version) like BinaryResource(id='riscv-hello', resource_version='1.0.0').
• Users can use GEM5_RESOURCE_JSON and GEM5_RESOURCE_JSON_APPEND env variables to overwrite all the data sources with the provided JSON and append a JSON file to all the data source respectively. More information can be found here.

Other user-facing changes

• Added support for clang 15 and clang 16
• gem5 no longer supports building on Ubuntu 18.04
• GCC 7, GCC 9, and clang 6 are no longer supported
• Two DRAMInterface stats have changed names (bytesRead and bytesWritten). For instance, board.memory.mem_ctrl.dram.bytesRead and board.memory.mem_ctrl.dram.bytesWritten. These are changed to dramBytesRead and dramBytesWritten so they don't collide with the stat with the same name in AbstractMemory.
• The stats for NVMInterface (bytesRead and bytesWritten) have been change to nvmBytesRead and nvmBytesWritten as well.

Full-system GPU model improvements

• Support for up to latest ROCm 5.7.1.
• Various changes to enable PyTorch/TensorFlow simulations.
• New packer disk image script containing ROCm 5.4.2, PyTorch 2.0.1, and Tensorflow 2.11.
• GPU instructions can now perform atomics on host addresses.
• The provided configs scripts can now run KVM on more restrictive setups.
• Add support to checkpoint and restore between kernels in GPUFS, including adding various AQL, HSA Queue, VMID map, MQD attributes, GART translations, and PM4Queues to GPU checkpoints
• move GPU cache recorder code to RubyPort instead of Sequencer/GPUCoalescer to allow checkpointing to occur
• add support for flushing GPU caches, as well as cache cooldown/warmup support, for checkpoints
• Update vega10_kvm.py to add checkpointing instructions

SE mode GPU model improvements

• started adding support for mmap'ing inputs for GPUSE tests, which reduces their runtime by 8-15% per run

GPU model improvements

• update GPU VIPER and Coalescer support to ensure correct replacement policy behavior when multiple requests from the same CU are concurrently accessing the same line
• fix bug with GPU VIPER to resolve a race conflict for loads that bypass the TCP (L1D$)
• fix bug with MRU replacement policy updates in GPU SQC (I$)
• update GPU and Ruby debug prints to resolve various small errors
• Add configurable GPU L1,L2 num banks and L2 latencies
• Add decodings for new MI100 VOP2 insts
• Add GPU GLC Atomic Resource Constraints to better model how atomic resources are shared at GPU TCC (L2$)
• Update GPU tester to work with both requests that bypass all caches (SLC) and requests that bypass only the TCP (L1D$)
• Fixes for how write mask works for GPU WB L2 caches
• Added support for WB and WT GPU atomics
• Added configurable support to better model the latency of GPU atomic requests
• fix GPU's default number of HW barrier/CU to better model amount of concurrency GPU CUs should have

RISC-V RVV 1.0 implemented

This was a huge undertaking by a large number of people!
Some of these people include Adrià Armejach who pushed it over the finish line, Xuan Hu who pushed the most recent version to gerrit that Adrià picked up,
Jerin Joy who did much of the initial work, and many others who contributed to the implementation including Roger Chang, Hoa Nguyen who put significant effort into testing and reviewing the code.

• Most of the instructions in the 1.0 spec implemented
• Works with both FS and SE mode
• Compatible with Simple CPUs, the O3, and the minor CPU models
• User can specify the width of the vector units
• Future improvements
  • Widening/narrowing instructions are not implemented
  • The model for executing memory instructions is not very high performance
  • The statistics are not correct for counting vector instruction execution

ArmISA changes/improvements

• Architectural support for the following extensions:

• FEAT_TLBIRANGE
• FEAT_FGT
• FEAT_TCR2
• FEAT_SCTLR2

• Arm support for SVE instructions improved
• Fixed some FEAT_SEL2 related issues:
  • Fix virtual interrupt logic in secure mode
  • Make interrupt masking handle VHE/SEL2 cases
• Removed support for Arm Jazelle and ThumbEE
• Implementation of an Arm Capstone Disassembler

Other notable changes/improvements

• Improvements to the CHI coherence protocol implementation
• Far atomics implemented in CHI
• Ruby now supports using the prefetchers from the classic caches, if the protocol supports it. CHI has been extended to support the classic prefetchers.
• Bug in RISC-V TLB to fixed to correctly count misses and hits
• Added new RISC-V Zcb instructions #399
• RISC-V can now use a separate binary for the bootloader and kernel in FS mode
• DRAMSys integration updated to latest DRAMSys version (5.0)
• Improved support for RISC-V privilege modes
• Fixed bug in switching CPUs with RISC-V
• CPU branch preditor refactoring to prepare for decoupled front end support
• Perf is now optional when using the KVM CPU model
• Improvements to the gem5-SST bridge including updating to SST 13.0
• Improved formatting of documentation in stdlib
• By default use isort for python imports in style
• Many, many testing improvements during the migration to GitHub actions
• Fixed the elastic trace replaying logic (TraceCPU)

Known Bugs/Issues

• RISC-V RVV Bad execution of riscv rvv vss instruction
• RISC-V Vector Extension float32_t bugs/unsupported widening instructions
• Implement AVX xsave/xstor to avoid workaround when checkpointing
• Adding Vector Segmented Loads/Stores to RISC-V V 1.0 implementation
• Integer overflow in AddrRange subset check
• RISCV64 TLB refuses to access upper half of physical address space
• Bug when trying to restore checkpoints in SPARC: “panic: panic condition !pte occurred: Tried to execute unmapped address 0.”
• BaseCache::recvTimingResp can trigger an assertion error from getTarget() due to MSHR in senderState having no targets

Version 23.0.1.0

This minor release incorporates documentation updates, bug fixes, and some minor improvements.

Documentation updates

• "TESTING.md" has been updated to more accurately reflect our current testing infrastructure.
• "README" has been replaced with "README.md" and includes more up-to-date information on using gem5.
• "CONTRIBUTING.md" has been updated to reflect our migration to GitHub and the changes in policy and proceedures.
• Where needed old references to Gerrit have been removed in favor of GitHub.

Bug Fixes

• Fixes an assert failure when using ARM which was trigged when shiftAmt is 0 for a UQRSH instruction.
• Fixes name 'fatal' is not defined being thrown when tracing is off.
• Fixes a bug in ARM in which the TLBIOS instructions were decoded as normal MSR instructions with no effect on the TLBs.
• Fixes invalid packet_id value in flit.
• Fixes default CustomMesh for use with Garnet.

Minor Improvements

• The gem5 resources downloader now outputs more helpful errors in the case of a failure.
• "util/github-runners-vagrant" has been added. This outlines how to setup a GitHub Action's set-hosted runner for gem5.
• The PyUnit tests have been refactored to no longer download large resources during testing.
• Using Perf is now optional when utilizing KVM CPUs.

Version 23.0.0.1

[HOTFIX] Fixes compilation of GCN3_X86 and VEGA_X85.

This hotfix release:

• Removes the use of 'std::random_shuffle'.
  This is a deprecated function in C++17 and has been removed in C++20.
• Adds missing 'overrides' in "src/arch/amdgpu/vega/insts/instructions.hh".
• Fixes Linux specific includes, allowing for compilation on non-linux systems.
• Adds a missing include in "src/gpu-compute/dispatcher.cc".

Version 23.0.0.0

This release has approximately 500 contributions from 50 unique contributors.
Below we highlight key gem5 features and improvements in this release.

Significant API and user-facing changes

Major renaming of CPU stats

The CPU stats have been renamed.
See https://gem5.atlassian.net/browse/GEM5-1304 for details.

Now, each stage (fetch, execute, commit) have their own stat group.
Stats that are shared between the different CPU model (O3, Minor, Simple) now have the exact same names.

Important: Some stat names were misleading before this change.
With this change, stats with the same names between different CPU models have the same meaning.

fs.py and se.py deprecated

These scripts have not been well supported for many gem5 releases.
With gem5 23.0, we have officially deprecated these scripts.
They have been moved into the deprecated directory, but they will be removed in a future release.
As a replacement, we strongly suggest using the gem5 standard library.
See https://www.gem5.org/documentation/gem5-stdlib/overview for more information.

Renaming of DEBUG guard into GEM5_DEBUG

Scons no longer defines the DEBUG guard in debug builds, so code making using of it should use GEM5_DEBUG instead.

Other API changes

Also, this release:

• Removes deprecated namespaces. Namespace names were updated a couple of releases ago. This release removes the old names.
• Uses MemberEventWrapper in favor of EventWrapper for instance member functions.
• Adds an extension mechanism to Packet and Request.
• Sets x86 CPU vendor string to "HygoneGenuine" to better support GLIBC.

New features and improvements

Large improvements to gem5 resources and gem5 resources website

We now have a new web portal for the gem5 resources: https://resources.gem5.org

This web portal will allow users to browse the resources available (e.g., disk images, kernels, workloads, binaries, simpoints, etc.) to use out-of-the-box with the gem5 standard library.
You can filter based on architecture, resource type, and compatible gem5 versions.

For each resource, there are examples of how to use the resource and pointers to examples using the resource in the gem5 codebase.

More information can be found on gem5's website: https://www.gem5.org/documentation/general_docs/gem5_resources/

We will be expanding gem5 resources with more workloads and resources over the course of the next release.
If you would like to contribute to gem5 resources by uploading your own workloads, disk images, etc., please create an issue on GitHub.

In addition to the new gem5 Resources web portal, the gem5 Resources API has been significantly updated and improved.
There are now much simpler functions for getting resources such as obtain_resource(<name>) that will download the resource by name and return a reference that can be used (e.g., as a binary in set_se_workload function on the board).
As such the generic Resouce class has been deprecated and will be removed in a future release.

Resources are now specialized for their particular category.
For example, there is now a BinaryResource class which will return if a user specifies a binary resource when using the obtain_resource function.
This allow for resource typing and for greater resource specialization.

Arm ISA improvements

Architectural support for Armv9 Scalable Matrix extension (FEAT_SME).
The implementation employs a simple renaming scheme for the Za array register in the O3 CPU, so that writes to difference tiles in the register are considered a dependency and are therefore serialized.

The following SVE and SIMD & FP extensions have also been implemented:

• FEAT_F64MM
• FEAT_F32MM
• FEAT_DOTPROD
• FEAT_I8MM

And more generally:

• FEAT_TLBIOS
• FEAT_FLAGM
• FEAT_FLAGM2
• FEAT_RNG
• FEAT_RNG_TRAP
• FEAT_EVT

Support for DRAMSys

gem5 can now use DRAMSys https://github.com/tukl-msd/DRAMSys as a DRAM backend.

RISC-V improvements

This release:

• Fully implements RISC-V scalar cryptography extensions.
• Fully implement RISC-V rv32.
• Implements PMP lock features.
• Adds general RISC-V improvements to provide better stability.

Standard library improvements and new components

This release:

• Adds MESI_Three_Level component.
• Supports ELFies and LoopPoint analysis output from Sniper.
• Supports DRAMSys in the stdlib.

Bugfixes and other small improvements

This release also:

• Removes deprecated python libraries.
• Adds a DDR5 model.
• Adds AMD GPU MI200/gfx90a support.
• Changes building so it no longer "duplicates sources" in build/ which improves support for some IDEs and code analysis. If you still need to duplicate sources you can use the --duplicate-sources option to scons.
• Enables --debug-activate=<object name> to use debug trace for only a single SimObject (the opposite of --debug-ignore). See --debug-help for more information.
• Adds support to exit the simulation loop based on Arm-PMU events.
• Supports Python 3.11.
• Adds the idea of a CpuCluster to gem5.

Version 22.1.0.0

This release has 500 contributions from 48 unique contributors and marks our second major release of 2022.
This release incorporates several new features, improvements, and bug fixes for the computer architecture reserach community.

See below for more details!

New features and improvements

• The gem5 binary can now be compiled to include multiple ISA targets.
  A compilation of gem5 which includes all gem5 ISAs can be created using: scons build/ALL/gem5.opt.
  This will use the Ruby MESI_Two_Level cache coherence protocol by default, to use other protocols: scons build/ALL/gem5.opt PROTOCOL=<other protocol>.
  The classic cache system may continue to be used regardless as to which Ruby cache coherence protocol is compiled.
• The m5 Python module now includes functions to set exit events are particular simululation ticks:
  • setMaxTick(tick) : Used to to specify the maximum simulation tick.
  • getMaxTick() : Used to obtain the maximum simulation tick value.
  • getTicksUntilMax(): Used to get the number of ticks remaining until the maximum tick is reached.
  • scheduleTickExitFromCurrent(tick) : Used to schedule an exit exit event a specified number of ticks in the future.
  • scheduleTickExitAbsolute(tick) : Used to schedule an exit event as a specified tick.
• We now include the RiscvMatched board as part of the gem5 stdlib.
  This board is modeled after the HiFive Unmatched board and may be used to emulate its behavior.
  See "configs/example/gem5_library/riscv-matched-fs.py" and "configs/example/gem5_library/riscv-matched-hello.py" for examples using this board.
• An API for SimPoints has been added.
  SimPoints can substantially improve gem5 Simulation time by only simulating representative parts of a simulation then extrapolating statistical data accordingly.
  Examples of using SimPoints with gem5 can be found in "configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py" and "configs/example/gem5_library/checkpoints/simpoints-se-restore.py".
• "Workloads" have been introduced to gem5.
  Workloads have been incorporated into the gem5 Standard library.
  They can be used specify the software to be run on a simulated system that come complete with input parameters and any other dependencies necessary to run a simuation on the target hardware.
  At the level of the gem5 configuration script a user may specify a workload via a board's set_workload function.
  For example, set_workload(Workload("x86-ubuntu-18.04-boot")) sets the board to use the "x86-ubuntu-18.04-boot" workload.
  This workload specifies a boot consisting of the Linux 5.4.49 kernel then booting an Ubunutu 18.04 disk image, to exit upon booting.
  Workloads are agnostic to underlying gem5 design and, via the gem5-resources infrastructure, will automatically retrieve all necessary kernels, disk-images, etc., necessary to execute.
  Examples of using gem5 Workloads can be found in "configs/example/gem5_library/x86-ubuntu-ruby.py" and "configs/example/gem5_library/riscv-ubuntu-run.py".
• To aid gem5 developers, we have incorporated pre-commit checks into gem5.
  These checks automatically enforce the gem5 style guide on Python files and a subset of other requirements (such as line length) on altered code prior to a git commit.
  Users may install pre-commit by running ./util/pre-commit-install.sh.
  Passing these checks is a requirement to submit code to gem5 so installation is strongly advised.
• A multiprocessing module has been added.
  This allows for multiple simulations to be run from a single gem5 execution via a single gem5 configuration script.
  Example of usage found in this commit message.
  Note: This feature is still in development.
  While functional, it'll be subject to subtantial changes in future releases of gem5.
• The stdlib's ArmBoard now supports Ruby caches.
• Due to numerious fixes and improvements, Ubuntu 22.04 can be booted as a gem5 workload, both in FS and SE mode.
• Substantial improvements have been made to gem5's GDB capabilities.
• The HBM2Stack has been added to the gem5 stdlib as a memory component.
• The MinorCPU has been fully incorporated into the gem5 Standard Library.
• We now allow for full-system simulation of GPU applications.
  The introduction of GPU FS mode allows for the same use-cases as SE mode but reduces the requirement of specific host environments or usage of a Docker container.
  The GPU FS mode also has improved simulated speed by functionally simulating memory copies, and provides an easier update path for gem5 developers.
  An X86 host and KVM are required to run GPU FS mode.

API (user facing) changes

• The default CPU Vendor String has been updated to HygonGenuine.
  This is due to newer versions of GLIBC being more strict about checking current system's supported features.
  The previous value, M5 Simulator, is not recognized as a valid vendor string and therefore GLIBC returns an error.
• The stdlib's _connect_things funciton call has been moved from the AbstractBoard's constructor to be run as board pre-instantiation process.
  This is to overcome instances where stdlib components (memory, processor, and cache hierarhcy) require Board information known only after its construction.
  This change breaks cases where a user utilizes the stdlib AbstractBoard but does not use the stdlib Simulator module. This can be fixed by adding the _pre_instantiate function before m5.instantiate.
  An exception has been added which explains this fix, if this error occurs.
• The setting of checkpoints has been moved from the stdlib's "set_workload" functions to the Simulator module.
  Setting of checkpoints via the stdlib's "set_workload" functions is now deprecated and will be removed in future releases of gem5.
• The gem5 namespace Trace has been renamed trace to conform to the gem5 style guide.
• Due to the allowing of multiple ISAs per gem5 build, the TARGET_ISA variable has been replaced with USE_$(ISA) variables.
  For example, if a build contains both the X86 and ARM ISAs the USE_X86 and USE_ARM variables will be set.

Big Fixes

• Several compounding bugs were causing bugs with floating point operations within gem5 simulations.
  These have been fixed.
• Certain emulated syscalls were behaving incorrectly when using RISC-V due to incorrect open(2) flag values.
  These values have been fixed.
• The GIVv3 List register mapping has been fixed.
• Access permissions for GICv3 cpu registers have been fixed.
• In previous releases of gem5 the sim_quantum value was set for all cores when using the Standard Library.
  This caused issues when setting exit events at a particular tick as it resulted in the exit being off by sim_quantum.
  As such, the sim_quantum value is only when using KVM cores.
• PCI ranges in VExpress_GEM5_Foundation fixed.
• The SwitchableProcessor processor has been fixed to allow switching to a KVM core.
  Previously the SwitchableProcessor only allowed a user to switch from a KVM core to a non-KVM core.
• The Standard Library has been fixed to permit multicore simulations in SE mode.
• A bug was fixed in the rcr X86 instruction.

Build related changes

• gem5 can now be compiled with Scons 4 build system.
• gem5 can now be compiled with Clang version 14 (minimum Clang version 6).
• gem5 can now be compiled with GCC Version 12 (minimum GCC version 7).

Other minor updates

• The gem5 stdlib examples in "configs/example/gem5_library" have been updated to, where appropriate, use the stdlib's Simulator module.
  These example configurations can be used for reference as to how Simulator module may be utilized in gem5.
• Granulated SGPR computation has been added for gfx9 gpu-compute.
• The stdlib statistics have been improved:
  • A get_simstats function has been added to access statistics from the Simulator module.
  • Statistics can be printed: print(simstats.board.core.some_integer).
• GDB ports are now specified for each workload, as opposed to per-simulation run.
• The m5 utility has been expanded to include "workbegin" and "workend" annotations.
  This can be added with m5 workbegin and m5 workend.
• A PrivateL1SharedL2CacheHierarchy has been added to the Standard Library.
• A GEM5_USE_PROXY environment variable has been added.
  This allows users to specify a socks5 proxy server to use when obtaining gem5 resources and the resources.json file.
  It uses the format <host>:<port>.
• The fastmodel support has been improved to function with Linux Kernel 5.x.
• The set_se_binary_workload function now allows for the passing of input parameters to a binary workload.
• A functional CHI cache hierarchy has been added to the gem5 Standard Library: "src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py".
• The RISC-V K extension has been added.
  It includes the following instructions:
  • Zbkx: xperm8, xperm4
  • Zknd: aes64ds, aes64dsm, aes64im, aes64ks1i, aes64ks2
  • Zkne: aes64es, aes64esm, aes64ks1i, aes64ks2
  • Zknh: sha256sig0, sha256sig1, sha256sum0, sha256sum1, sha512sig0, sha512sig1, sha512sum0, sha512sum1
  • Zksed: sm4ed, sm4ks
  • Zksh: sm3p0, sm3p1

Version 22.0.0.2

[HOTFIX] This hotfix contains a set of critical fixes to be applied to gem5 v22.0.
This hotfix:

• Fixes the ARM booting of Linux kernels making use of FEAT_PAuth.
• Removes incorrect requires functions in AbstractProcessor and AbstractGeneratorCore.
  These requires were causing errors when running generators with any ISA other than NULL.
• Fixes the standard library's set_se_binary_workload function to exit on Exit Events (work items) by default.
• Connects a previously unconnected PCI port in the example SST RISC-V config to the membus.
• Updates the SST-gem5 README with the correct download links.
• Adds a getAddrRanges function to the HBMCtrl.
  This ensures the XBar connected to the controller can see the address ranges covered by both pseudo channels.
• Fixes test_download_resources.py so the correct parameter is passed to the download test script.

Version 22.0.0.1

[HOTFIX] Fixes relative import in "src/python/gem5/components/processors/simple_core.py".

The import from python.gem5.utils.requires import requires in v22.0.0.0 of gem5 is incorrect as it causes problems when executing gem5 binaries in certain directories (python isn't necessary included).
To resolve this, this import has been changed to from ...utils.requires imports requires.
This should work in all supported use-cases.

Version 22.0.0.0

gem5 version 22.0 has been slightly delayed, but we a have a very strong release!
This release has 660 changes from 48 unique contributors.
While there are not too many big ticket features, the community has done a lot to improve the stablity and add bugfixes to gem5 over this release.
That said, we have a few cool new features like full system GPU support, a huge number of Arm improvements, and an improved HBM model.

See below for more details!

New features

• Arm now models DVM messages for TLBIs and DSBs accurately. This is implemented in the CHI protocol.
• EL2/EL3 support on by default in ArmSystem
• HBM controller which supports pseudo channels
• Improved Ruby's SimpleNetwork routing
• Added x86 bare metal workload and better real mode support
• Added round-robin arbitration when using multiple prefetchers
• KVM Emulation added for ARM GIGv3
• Many improvements to the CHI protocol

Many RISC-V instructions added

The following RISCV instructions have been added to gem5's RISC-V ISA:

• Zba instructions: add.uw, sh1add, sh1add.uw, sh2add, sh2add.uw, sh3add, sh3add.uw, slli.uw
• Zbb instructions: andn, orn, xnor, clz, clzw, ctz, ctzw, cpop, cpopw, max, maxu, min, minu, sext.b, sext.h, zext.h, rol, rolw, ror, rori, roriw, rorw, orc.b, rev8
• Zbc instructions: clmul, clmulh, clmulr
• Zbs instructions: bclr, bclri, bext, bexti, binv, binvi, bset, bseti
• Zfh instructions: flh, fsh, fmadd.h, fmsub.h, fnmsub.h, fnmadd.h, fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fsgnj.h, fsgnjn.h, fsgnjx.h, fmin.h, fmax.h, fcvt.s.h, fcvt.h.s, fcvt.d.h, fcvt.h.d, fcvt.w.h, fcvt.h.w, fcvt.wu.h, fcvt.h.wu

Improvements to the stdlib automatic resource downloader

The gem5 standard library's downloader has been re-engineered to more efficiently obtain the resources.json file.
It is now cached instead of retrieved on each resource retrieval.

The resources.json directory has been moved to a more permament URL at http://resources.gem5.org/resources.json.

Tests have also been added to ensure the resources module continues to function correctly.

gem5 in SystemC support revamped

The gem5 in SystemC has been revamped to accomodate new research needs.
These changes include stability improvements and bugs fixes.
The gem5 testing suite has also been expanded to include gem5 in SystemC tests.

Improved GPU support

Users may now simulate an AMD GPU device in full system mode using the ROCm 4.2 compute stack.
Until v21.2, gem5 only supported GPU simulation in Syscall-Emulation mode with ROCm 4.0.
See src/gpu-fs/README.md in gem5-resources and example scripts in configs/example/gpufs/ for example scripts which run GPU full system simulations.

A GPU Ruby random tester has been added to help validate the correctness of the CPU and GPU Ruby coherence protocols as part of every kokoro check-in.
This helps validate the correctness of the protocols before new changes are checked in.
Currently the tester focuses on the protocols used with the GPU, but the ideas are extensible to other protocols.
The work is based on "Autonomous Data-Race-Free GPU Testing", IISWC 2019, Tuan Ta, Xianwei Zhang, Anthony Gutierrez, and Bradford M. Beckmann.

An Arm board has been added to the gem5 Standard Library

Via this change, an ARM Board, ArmBoard, has been added to the gem5 standard library.
This allows for an ARM system to be run using the gem5 stdlib components.

An example gem5 configuration script using this board can be found in configs/example/gem5_library/arm-ubuntu-boot-exit.py.

createAddrRanges now supports NUMA configurations

When the system is configured for NUMA, it has multiple memory ranges, and each memory range is mapped to a corresponding NUMA node. For this, the change enables createAddrRanges to map address ranges to only a given HNFs.

Jira ticker here: https://gem5.atlassian.net/browse/GEM5-1187.

API (user-facing) changes

CPU model types are no longer simply the model name, but they are specialized for each ISA

For instance, the O3CPU is now the X86O3CPU and ArmO3CPU, etc.
This requires a number of changes if you have your own CPU models.
See https://gem5-review.googlesource.com/c/public/gem5/+/52490 for details.

Additionally, this requires changes in any configuration script which inherits from the old CPU types.

In many cases, if there is only a single ISA compiled the old name will still work.
However, this is not 100% true.

Finally, CPU_MODELS is no longer a parameter in build_opts/.
Now, if you want to compile a CPU model for a particular ISA you will have to add a new file for the CPU model in the arch/ directory.

Many changes in the CPU and ISA APIs

If you have any specialized CPU models or any ISAs which are not in the mainline, expect many changes when rebasing on this release.

• No longer use read/setIntReg (e.g., see https://gem5-review.googlesource.com/c/public/gem5/+/49766)
• InvalidRegClass has changed (e.g., see https://gem5-review.googlesource.com/c/public/gem5/+/49745)
• All of the register classes have changed (e.g., see https://gem5-review.googlesource.com/c/public/gem5/+/49764/)
• initiateSpecialMemCmd renamed to initiateMemMgmtCmd to generalize to other command beyond HTM (e.g., DVM/TLBI)
• OperandDesc class added (e.g., see https://gem5-review.googlesource.com/c/public/gem5/+/49731)
• Many cases of TheISA have been removed

Bug Fixes

• Fixed RISC-V call/ret instruction decoding. The fix adds IsReturnandIsCallflags for RISC-V jump instructions by defining a newJumpConstructor` in "standard.isa". Jira Ticket here: https://gem5.atlassian.net/browse/GEM5-1139.
• Fixed x86 Read-Modify-Write behavior in multiple timing cores with classic caches. Jira Ticket here: https://gem5.atlassian.net/browse/GEM5-1105.
• The circular buffer for the O3 LSQ has been fixed. This issue affected running the O3 CPU with large workloaders. Jira Ticket here: https://gem5.atlassian.net/browse/GEM5-1203.
• Removed "memory-leak"-like error in RISC-V lr/sc implementation. Jira issue here: https://gem5.atlassian.net/browse/GEM5-1170.
• Resolved issues with Ruby's memtest. In gem5 v21.2, If the size of the address range was smaller than the maximum number of outstandnig requests allowed downstream, the tester would get stuck trying to find a unique address. This has been resolved.

Build-related changes

• Variable in env in the SConscript files now requires you to use env['CONF'] to access them. Anywhere that env['<VARIABLE>'] appeared should noe be env['CONF']['<VARIABLE>']
• Internal build files are now in a per-target gem5.build directory
• All build variable are per-target and there are no longer any shared variables.

Other changes

• New bootloader is required for Arm VExpress_GEM5_Foundation platform. See https://gem5.atlassian.net/browse/GEM5-1222 for details.
• The MemCtrl interface has been updated to use more inheritance to make extending it to other memory types (e.g., HBM pseudo channels) easier.

Version 21.2.1.1

[HOTFIX] In order to ensure v21 of gem5 remains compatible with future changes, the gem5 stdlib downloader has been updated to obtain the resources.json file from https://resources.gem5.org/resources.json.
As this domain is under the gem5 project control, unlike the previous googlesource URL, we can ensure longer-term stability.
The fix also ensures the downloader can parse plain-text JSON and base64 encoding of the resources.json file.

Version 21.2.1.0

Version 21.2.1 is a minor gem5 release consisting of bug fixes. The 21.2.1 release:

• Fixes a bug in which a RCV instruction is wrongly regarded as a branch.
• Removes outdated and incomplete standard library documentation.
  Users wishing to learn more about the gem5 standard library should consult materials on the gem5 website.
• Adds a VirtIO entropy device (VirtIORng) to RISC-V.
  Without this, RISCV Disk images can take considerable time to boot and occasionally do so in error.
• Removes the 'typing.final' decorator from the standard library.
  'typing.final' was introduced in Python 3.8, but v21.2 of gem5 supports Python 3.6.
• Fixes the broken NPB stdlib example test.