Bugfix: enable USART internal clock mode on init.

* Added DMA support
* Uart tx and rx fields are now public instead of split()/join() methods.

* Doc fixes in v2::{uart, spi}
* Remove dead code warning in dmac::channel::reg.rs
* BEAT -> BURST DMAC trigger (thumbv7em)
* Add deprecation warnings for v1::{uart, spi} (thumbv6m and
  thumbv7em)

The `sercom::v2::Pad` type was a simple wrapper around a `gpio::v2::Pin`
type. Its purpose was to ensure that each `Pin` was properly configured
to act as the corresponding SERCOM `Pad`. However, one of my goals in
designing the `v2::spi` API was to avoid the need for users to manually
convert `Pin` types to `Pad` types. As that module progressed, it became
clear that the `v2::Pad` type served no real purpose. All the same
constraints could be imposed using a slightly different approach to
type-level programming.

Remove the `v2::Pad` type and modify the `sercom::v2::pad` module
accordingly. Update the `v1::Pad` type as well. Rename some of the
type-level items in the `v2::pad` module and improve the documentation.
Update the `sercom::v1` peripheral APIs to accept both `v1::Pad` types
and the equivalent of a `v2::Pad`, which is simply a properly configured
`v2::Pin`.

* Change UartRx/UartTx to a unified Uart struct (with
  capability-dictating type parameter)
* Add Capability, Transmit, Receive, Simplex traits
* Implement AsMut<Reconfig> for (&mut Uart<C, RxDuplex>, &mut Uart<C,
  TxDuplex>) to allow reconfiguring without needing to move Rx/Tx halves
  into a Uart<C, Duplex>
* Split some code into submodules
* Add RegisterInterface trait to help with some register accesses
* Update docs

The `sercom::v2::Pad` type was a simple wrapper around a `gpio::v2::Pin`
type. Its purpose was to ensure that each `Pin` was properly configured
to act as the corresponding SERCOM `Pad`. However, one of my goals in
designing the `v2::spi` API was to avoid the need for users to manually
convert `Pin` types to `Pad` types. As that module progressed, it became
clear that the `v2::Pad` type served no real purpose. All the same
constraints could be imposed using a slightly different approach to
type-level programming.

Remove the `v2::Pad` type and modify the `sercom::v2::pad` module
accordingly. Update the `v1::Pad` type as well. Rename some of the
type-level items in the `v2::pad` module and improve the documentation.
Update the `sercom::v1` peripheral APIs to accept both `v1::Pad` types
and the equivalent of a `v2::Pad`, which is simply a properly configured
`v2::Pin`.

Finally, redefine the type parameters of `v2::spi::Pads` to be
`OptionalPad`s rather than `OptionalPinId`s, and provide a new
`PadsFromIds` to make up for it. This change increases consistency in
the definition of the `spi::Pads` type, and it allows me to remove a
significant amount of trait boilerplate needed to make it all work.

Merge UART implementations into single top-level sercom module
Change RegisterInterface trait to Registers struct

For thumbv7em targets: it was possible to have [u8; length] as a valid
DMA beat. Adds the AtomicLength, which restricts DMA transactions to
single u8, u16 or u32 words.

Updated feather_m0 and feather_m4 BSPs and added uart examples

Remove Reconfig struct and ReadConfig trait

…t-v2

…t-v2

Improve CharSize API
Registers methods take Flags and Status structs instead of raw bits
Remove From implementations for StopBits, BitOrder, Baud, etc.

RXEN/TXEN will only be enabled if the underlying Pads have RX/TX
capability.

…t-v2

Move BITS constant from CharSize to FixedCharSize trait and rename to
SIZE