Make a new syntax node for modules

[thiskappaisgrey]

For the decompilation application, we need to turn the modules that we find back into verilog instantiations of the module (i.e. unflatten). Right now, I instantiate my module like:

(function ALU ( Expr  Expr Expr ) Expr :cost 0)

which is the "simplest" solution for now. However, I'd need to be able to turn this expression:

(ALU i_bit1 i_bit2 i_op) 

Into the verilog:

// may probably need to declare a wire for the output of the ALU or something
wire o_out;
alu alu(
           .i_a (o_a), 
          .i_b (o_b),
          .i_control (i_op),
          .o_res (o_out)
          );

when we do the decompilation and turn the Egglog expression back into the verilog again.

There are probably some other complications with this - but this is the idea for now.