Investigate possible impact of $shiftx vs. $shr

[ninehusky]

According to the Yosys documentation:

The $shift cell performs a right logical shift if the second operand is positive (or unsigned), and a left logical shift if it is negative. The $shiftx cell performs the same operation as the $shift cell, but the vacated bit positions are filled with undef (x) bits, and corresponds to the Verilog indexed part-select expression.

Because Churchroad doesn't support X bits, for now we'll encode both to a regular right shift, but this is something to potentially keep in mind.

[gussmith23]

This eventually came up. I posted a discussion question here:
YosysHQ/yosys#4342

Essentially, any time we have an indexing expression in Verilog (e.g. INIT[idx] in LUT6), we'll get $shiftx. I don't think we actually want $shiftx in Churchroad, because its semantics are more complicated than standard shifts. It's not that complicated, but I would still like to avoid it if possible.