Ensure that the design is in a sane state before generating Churchroad output with write_churchroad

[gussmith23]

We currently run some passes (splice; splitnets -driver; clean) to put the design into a certain state before generating output. We should explicitly check that the design meets certain requirements before generating output, though.

[thiskappaisgrey]

Oh yeah,
Sometimes I needed to do it twice before it completely gets rid of the splitwise assignments.
i.e. run write_verilog synth.v and then load synth.v into yosys and run splitnets on it again for it to work.