rtl-design

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

makefile verilog synthesis systemverilog hdl testbench systemverilog-hdl systemverilog-simulation rtl-design systemverilog-test-bench edge-detector-with-mealy

Updated Nov 6, 2022
SystemVerilog

Akashtailor-exe / 30-days-of-verilog

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30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

verilog vlsi 30daysofcode 30-days-of-code digital-logic-design verilog-programs digitalcircuit verilog-project rtl-design rtl-coding

Updated Sep 30, 2023

synogate / gatery

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Gatery, a library for circuit design.

library asic fpga cpp rtl vlsi vlsi-design rtl-design gatery

Updated Aug 15, 2023
C++

maazm007 / 100Daysof_RTL

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The Repository contains the code of various Digital Circuits

verilog hdl verilog-hdl xilinx-ise vlsi-design rtl-design

Updated Aug 7, 2023
Verilog

esynr3z / pip-hdl

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📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

python vhdl verification vip pip verilog systemverilog ip-core rtl-design

Updated Jan 26, 2024
Python

synogate / gatery_template

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Template project for using gatery

asic fpga cpp rtl vlsi vlsi-design rtl-design gatery

Updated Aug 15, 2023
C++

Luca-Dalmasso / DLX

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RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor

vhdl embedded-systems hardware-designs computer-architecture dlx digital-design risc-processor dlx-instruction-set rtl-design dlx-processor

Updated Dec 22, 2022
Verilog

Farbod-Siahkali / Digital-Logical-Designs-Projects

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Digital Logical Designs Course Projects

state-machine rtl gate-level-simulation rtl-design dld-project

Updated Aug 19, 2022
Verilog

williaml33moore / bathtub

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BDD Gherkin implementation in native SystemVerilog, based on UVM.

asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification

Updated Apr 27, 2024
SystemVerilog

alirezajaberirad / Object-Oriented-Modeling-of-Electronic-Circuits

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This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022

image-processing object-oriented systemc object-oriented-programming gate-level system-modeling systemc-ams gate-level-simulation rtl-design

Updated Jul 29, 2022
C++

Mhd-Shah / Verification-of-D--flipflop-using-UVM

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Verification of D-FF using UVM on EDA playground

verilog systemverilog verilog-hdl dflipflop rtl-design uvm-verification

Updated Nov 19, 2023
SystemVerilog

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

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This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

rtl verilog finite-state-machine synthesis vivado systemverilog questasim testbench rtl-design