An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

A Verilog HDL Guide for Beginners.

acadamic course in campus il about building a modern computer from basic logic gates such as "nand" to a general computer architecture that is designed execute any program such as "Tetris". and also building assambler

Optimized 32-Bit Full Adder, CEC-SAT Verifier & 2-SAT Solver

Digital System Design Verilog Implementation

A Diode-Transistor-Logic Adder System built from Scratch, with simplicity and robustness in mind

This repository contains project done in LabView IDE from Basic Gates designing, Adders, Counters, Encoders, Decoders and Examples to connect to external Arduino like embedded systems

Different adders code in VHDL and Comparison

A digital design for a carry select adder

Tree adder for fast addition

Progetti di Elettronica Digitale 2021.

Useful VHDL scripts for hardware description.

Repository containing digital circuit projects developed for the INF01058 course at UFRGS.

In this project, I conducted an in-depth comparative analysis of various adder architectures to assess their performance in terms of delay and power consumption.

design and tb for 32-bit kogge stone adder