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vsetvli
vector tail agnostic and vector mask agnostic operands are mandatory
#489
opened May 23, 2024 by
ThinkOpenly
Sail-riscv uses only 1 cpu thread at a time thus slowing down the compilaton.
#487
opened May 23, 2024 by
Mudassir10X
VM code doesn't check reserved bits of PTEs are zero
bug
Something isn't working
configuration
Additional configuration settings needed for the model
#457
opened Apr 24, 2024 by
Timmmm
Implementing callbacks in sail-riscv for state-changing events
enhancement
New feature or request
refactor
Code clean up
#449
opened Apr 12, 2024 by
kseniadobrovolskaia
Use newtype for physical and virtual addresses
refactor
Code clean up
#434
opened Mar 18, 2024 by
Timmmm
Use result type instead of Code clean up
MemoryOpResult
, TR_Result
, and PTW_Result
refactor
#433
opened Mar 15, 2024 by
Timmmm
Refactor duplicated floating point code for 16/32/64 bit floats
refactor
Code clean up
#432
opened Mar 13, 2024 by
Timmmm
Remove redundant match expressions for word width
refactor
Code clean up
#429
opened Mar 11, 2024 by
Timmmm
Support for SystemVerilog compilation using sail -sv
enhancement
New feature or request
#424
opened Mar 4, 2024 by
torjeikenes
Add comment explaining why the model doesn't use vectors for registers
refactor
Code clean up
#409
opened Feb 19, 2024 by
Timmmm
is_CSR_defined has redundant privilege mode checks
refactor
Code clean up
#402
opened Feb 6, 2024 by
Timmmm
Another vector test suite, maybe add this to CI?
configuration
Additional configuration settings needed for the model
enhancement
New feature or request
#391
opened Jan 18, 2024 by
cfbolz
Logging state changes
enhancement
New feature or request
refactor
Code clean up
#390
opened Jan 16, 2024 by
allenjbaum
More rigorous handling of reset
bug
Something isn't working
refactor
Code clean up
#383
opened Jan 4, 2024 by
Timmmm
32-bit vs. 34-bit physical addresses in RV32 (without/with Sv32)
bug
Something isn't working
#378
opened Dec 18, 2023 by
rsnikhil
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Updated in the last three days: updated:>2024-05-31.