adapted for changes to introduce register file layer

rggen · Jun 1, 2020 · 66f8fc0 · 66f8fc0
1 parent 09def2f
commit 66f8fc0
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Showing 6 changed files with 16 additions and 16 deletions.
diff --git a/lib/rggen/systemverilog/common.rb b/lib/rggen/systemverilog/common.rb
@@ -28,10 +28,10 @@ module Common
       def self.register_component(builder, name, feature_class)
         builder.output_component_registry(name) do
           register_component [
-            :register_map, :register_block, :register, :bit_field
+            :root, :register_block, :register_file, :register, :bit_field
           ] do |category|
             component Component, ComponentFactory
-            feature feature_class, FeatureFactory if category != :register_map
+            feature feature_class, FeatureFactory if category != :root
           end
         end
       end

diff --git a/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb b/lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
@@ -11,7 +11,7 @@
     end
 
     build do
-      if register.bit_fields?
+      unless register.bit_fields.empty?
         interface :register, :bit_field_if, {
           name: 'bit_field_if',
           interface_type: 'rggen_bit_field_if',

diff --git a/spec/rggen/systemverilog/common/component_spec.rb b/spec/rggen/systemverilog/common/component_spec.rb
@@ -2,19 +2,19 @@
 
 RSpec.describe RgGen::SystemVerilog::Common::Component do
   let(:configuration) do
-    RgGen::Core::Configuration::Component.new('configuration', nil)
+    RgGen::Core::Configuration::Component.new(nil, 'configuration', nil)
   end
 
   let(:register_map) do
-    RgGen::Core::RegisterMap::Component.new('register_map', nil, configuration)
+    RgGen::Core::RegisterMap::Component.new(nil, 'register_map', nil, configuration)
   end
 
   let(:component) do
-    described_class.new('component', nil, configuration, register_map)
+    described_class.new(nil, 'component', nil, configuration, register_map)
   end
 
   def create_child_component
-    described_class.new('component', component, configuration, register_map) do |child_component|
+    described_class.new(component, 'component', nil, configuration, register_map) do |child_component|
       component.add_child(child_component)
       yield(child_component)
     end

diff --git a/spec/rggen/systemverilog/common/feature_spec.rb b/spec/rggen/systemverilog/common/feature_spec.rb
@@ -2,15 +2,15 @@
 
 RSpec.describe RgGen::SystemVerilog::Common::Feature do
   let(:configuration) do
-    RgGen::Core::Configuration::Component.new('configuration', nil)
+    RgGen::Core::Configuration::Component.new(nil, 'configuration', nil)
   end
 
   let(:register_map) do
-    RgGen::Core::RegisterMap::Component.new('register_map', nil, configuration)
+    RgGen::Core::RegisterMap::Component.new(nil, 'register_map', nil, configuration)
   end
 
   let(:component) do
-    RgGen::Core::OutputBase::Component.new('component', nil, configuration, register_map)
+    RgGen::Core::OutputBase::Component.new(nil, 'component', nil, configuration, register_map)
   end
 
   def create_feature(&body)

diff --git a/spec/rggen/systemverilog/ral/feature_spec.rb b/spec/rggen/systemverilog/ral/feature_spec.rb
@@ -2,15 +2,15 @@
 
 RSpec.describe RgGen::SystemVerilog::RAL::Feature do
   let(:configuration) do
-    RgGen::Core::Configuration::Component.new('configuration', nil)
+    RgGen::Core::Configuration::Component.new(nil, 'configuration', nil)
   end
 
   let(:register_map) do
-    RgGen::Core::RegisterMap::Component.new('register_map', nil, configuration)
+    RgGen::Core::RegisterMap::Component.new(nil, 'register_map', nil, configuration)
   end
 
   let(:component) do
-    RgGen::Core::OutputBase::Component.new('component', nil, configuration, register_map)
+    RgGen::Core::OutputBase::Component.new(nil, 'component', nil, configuration, register_map)
   end
 
   let(:feature) do

diff --git a/spec/rggen/systemverilog/rtl/feature_spec.rb b/spec/rggen/systemverilog/rtl/feature_spec.rb
@@ -2,15 +2,15 @@
 
 RSpec.describe RgGen::SystemVerilog::RTL::Feature do
   let(:configuration) do
-    RgGen::Core::Configuration::Component.new('configuration', nil)
+    RgGen::Core::Configuration::Component.new(nil, 'configuration', nil)
   end
 
   let(:register_map) do
-    RgGen::Core::RegisterMap::Component.new('register_map', nil, configuration)
+    RgGen::Core::RegisterMap::Component.new(nil, 'register_map', nil, configuration)
   end
 
   let(:component) do
-    RgGen::Core::OutputBase::Component.new('component', nil, configuration, register_map)
+    RgGen::Core::OutputBase::Component.new(nil, 'component', nil, configuration, register_map)
   end
 
   let(:feature) do