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FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.

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quartiq/bscan_spi_bitstreams

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bscan_spi_bitstreams

JTAG-SPI proxy bitstreams to be used with the OpenOCD jtagspi flash driver -- but potentially other JTAG software as well. These bitstreams have been tested on the KC705, Pipistrello, Kasli, Sayma-AMC+Sayma-RTM, Lattice ECP5 Versa and several other boards.

Currently, bitstreams for Xilinx and Lattice chips are generated with the following scripts:

  • xilinx_bscan_spi.py: (o)Migen script that generates bitstreams for Xilinx chips; all the generated .bit bistreams are contained in this repository.
  • lattice_bscan_spi.py: nMigen script that generates bitstreams for Lattice chips; a .svf JTAG programming vector generated for LFE5UM-45F is currently contained in this repository.
    • Note on usage: After programming the device through JTAG, the reset halt command is required before performing flash commands on OpenOCD. Also note that when using jtagspi, the private instruction 0x32 must be shifted into the JTAG IR on Lattice FPGAs (see item "ER1, ER2" on p.758 of the FPGA Libraries Reference Guide 3.11 for details).

Versions

Note: The bitstreams in this branch require openocd as of 867bdb2 or later. Since 2017-08-08 and as of 2019-06-11 there has not been an openocd release including this.

Note: Bitstreams for previous openocd releases are in the single-tap branch.

Run

python3 -m venv --system-site-packages .venv
./.venv/bin/pip install -r requirements.txt
PATH=$PATH:/opt/Xilinx/Vivado/2022.2/bin:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64 ./.venv/bin/python3 xilinx_bscan_spi.py -p 16

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FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.

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