Improve NASM lexer (#2212)

Adds support for SSE/AVX/AVX-512 registers and 'rel' and 'abs' address
operators.

pygments/lexers/asm.py

@@ -730,8 +730,9 @@ class NasmLexer(RegexLexer):
     declkw = r'(?:res|d)[bwdqt]|times'
     register = (r'(r[0-9][0-5]?[bwd]?|'
                 r'[a-d][lh]|[er]?[a-d]x|[er]?[sb]p|[er]?[sd]i|[c-gs]s|st[0-7]|'
-                r'mm[0-7]|cr[0-4]|dr[0-367]|tr[3-7])\b')
-    wordop = r'seg|wrt|strict'
+                r'mm[0-7]|cr[0-4]|dr[0-367]|tr[3-7]|k[0-7]|'
+                r'[xyz]mm(?:[12][0-9]?|3[01]?|[04-9]))\b')
+    wordop = r'seg|wrt|strict|rel|abs'
     type = r'byte|[dq]?word'
     # Directives must be followed by whitespace, otherwise CPU will match
     # cpuid for instance.
@@ -778,7 +779,7 @@ class NasmLexer(RegexLexer):
             (r'#.*', Comment.Single)
         ],
         'punctuation': [
-            (r'[,():\[\]]+', Punctuation),
+            (r'[,{}():\[\]]+', Punctuation),
             (r'[&|^<>+*/%~-]+', Operator),
             (r'[$]+', Keyword.Constant),
             (wordop, Operator.Word),

tests/examplefiles/nasm/nasm_simd.asm

@@ -0,0 +1,13 @@
+; test source for SIMD operations
+; not intended to be executable
+bits 64
+
+kmovq k1, [rel mask]
+vpxor xmm0, xmm0, xmm0
+vmovdqa32 zmm30, [abs data]
+vpaddd zmm0{k1}, zmm0, zmm30
+vpxor xmm1, xmm1, [rel xmm01]
+
+mask dq 0xAAAAAAAA55555555
+data: times 16 dd 0x12345678
+xmm01: times 4 dd 0