Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

TST: Add CPU Dispatch test for RISC-V Vector Extenson. #26300

Open
wants to merge 1 commit into
base: main
Choose a base branch
from

Conversation

ArielHeleneto
Copy link

See #26219 .

This test check if RVV CPU feature can be detected susscessfully.

@ArielHeleneto
Copy link
Author

Hi should I at someone to check this PR or something?

@Mousius Mousius added the component: SIMD Issues in SIMD (fast instruction sets) code or machinery label May 6, 2024
@r-devulap
Copy link
Member

@ArielHeleneto could you fix the failing lint tests please?

@r-devulap r-devulap self-assigned this May 8, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
05 - Testing component: SIMD Issues in SIMD (fast instruction sets) code or machinery
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

3 participants