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update bitflags dep to 2.0
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add missing XCR0 & IA32_XSS bits
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@gz
semiviral authored and gz committed Apr 17, 2023
1 parent 898d010 commit 3f6e8b1
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Showing 4 changed files with 90 additions and 40 deletions.
16 changes: 8 additions & 8 deletions Cargo.toml
View file
Expand Up @@ -26,15 +26,15 @@ serialize = ["serde", "serde_derive"]
cli = ["display", "clap"]

[dependencies]
bitflags = "1.2"
serde = {version = "1.0", default-features = false, optional = true}
serde_derive = {version = "1.0", optional = true}
serde_json = {version = "1.0", optional = true}
termimad = {version = "0.21", optional = true}
clap = {version = "3.1.6", features = ["derive"], optional = true}
bitflags = { version = "2.0", features = ["serde"] }
serde = { version = "1.0", default-features = false, optional = true }
serde_derive = { version = "1.0", optional = true }
serde_json = { version = "1.0", optional = true }
termimad = { version = "0.21", optional = true }
clap = { version = "3.1.6", features = ["derive"], optional = true }

[target.'cfg(unix)'.dev-dependencies]
core_affinity = "0.8.0"
libc = {version = "0.2", default-features = false}
phf = {version = "0.11", features = ["macros"]}
libc = { version = "0.2", default-features = false }
phf = { version = "0.11", features = ["macros"] }
rustversion = "1.0"
34 changes: 25 additions & 9 deletions src/extended.rs
View file
Expand Up @@ -385,7 +385,9 @@ impl Debug for ExtendedProcessorFeatureIdentifiers {
}

bitflags! {
struct ExtendedFunctionInfoEcx: u32 {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct ExtendedFunctionInfoEcx: u32 {
const LAHF_SAHF = 1 << 0;
const CMP_LEGACY = 1 << 1;
const SVM = 1 << 2;
Expand Down Expand Up @@ -415,7 +417,9 @@ bitflags! {
}

bitflags! {
struct ExtendedFunctionInfoEdx: u32 {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct ExtendedFunctionInfoEdx: u32 {
const SYSCALL_SYSRET = 1 << 11;
const EXECUTE_DISABLE = 1 << 20;
const MMXEXT = 1 << 22;
Expand Down Expand Up @@ -1003,7 +1007,9 @@ impl ApmInfo {
}

bitflags! {
struct ApmInfoEdx: u32 {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct ApmInfoEdx: u32 {
const TS = 1 << 0;
const FID = 1 << 1;
const VID = 1 << 2;
Expand All @@ -1020,7 +1026,9 @@ bitflags! {
}

bitflags! {
struct RasCapabilities: u32 {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct RasCapabilities: u32 {
const MCAOVFLRECOV = 1 << 0;
const SUCCOR = 1 << 1;
const HWA = 1 << 2;
Expand Down Expand Up @@ -1169,7 +1177,7 @@ impl ProcessorCapacityAndFeatureInfo {

/// Performance time-stamp counter size (in bits).
///
/// Indicates the size of `MSRC001_0280[PTSC]`.
/// Indicates the size of `MSRC001_0280[PTSC]`.
///
/// # Platforms
/// ✅ AMD ❌ Intel (reserved=false)
Expand Down Expand Up @@ -1273,7 +1281,9 @@ impl Debug for ProcessorCapacityAndFeatureInfo {
}

bitflags! {
struct ProcessorCapacityAndFeatureEbx: u32 {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct ProcessorCapacityAndFeatureEbx: u32 {
const CLZERO = 1 << 0;
const INST_RETCNT_MSR = 1 << 1;
const RSTR_FP_ERR_PTRS = 1 << 2;
Expand Down Expand Up @@ -1421,7 +1431,9 @@ impl SvmFeatures {
}

bitflags! {
struct SvmFeaturesEdx: u32 {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct SvmFeaturesEdx: u32 {
const NP = 1 << 0;
const LBR_VIRT = 1 << 1;
const SVML = 1 << 2;
Expand Down Expand Up @@ -1555,7 +1567,9 @@ impl PerformanceOptimizationInfo {
}

bitflags! {
struct PerformanceOptimizationInfoEax: u32 {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct PerformanceOptimizationInfoEax: u32 {
const FP128 = 1 << 0;
const MOVU = 1 << 1;
const FP256 = 1 << 2;
Expand Down Expand Up @@ -1738,7 +1752,9 @@ impl MemoryEncryptionInfo {
}

bitflags! {
struct MemoryEncryptionInfoEax: u32 {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct MemoryEncryptionInfoEax: u32 {
const SME = 1 << 0;
const SEV = 1 << 1;
const PAGE_FLUSH_MSR = 1 << 2;
Expand Down
56 changes: 46 additions & 10 deletions src/lib.rs
View file
Expand Up @@ -401,9 +401,9 @@ impl<R: CpuIdReader> CpuId<R> {
vendor: self.vendor,
eax: res.eax,
ebx: res.ebx,
edx_ecx: FeatureInfoFlags {
bits: (((res.edx as u64) << 32) | (res.ecx as u64)),
},
edx_ecx: FeatureInfoFlags::from_bits_truncate(
((res.edx as u64) << 32) | (res.ecx as u64),
),
})
} else {
None
Expand Down Expand Up @@ -500,9 +500,9 @@ impl<R: CpuIdReader> CpuId<R> {
if self.leaf_is_supported(EAX_THERMAL_POWER_INFO) {
let res = self.read.cpuid1(EAX_THERMAL_POWER_INFO);
Some(ThermalPowerInfo {
eax: ThermalPowerFeaturesEax { bits: res.eax },
eax: ThermalPowerFeaturesEax::from_bits_truncate(res.eax),
ebx: res.ebx,
ecx: ThermalPowerFeaturesEcx { bits: res.ecx },
ecx: ThermalPowerFeaturesEcx::from_bits_truncate(res.ecx),
_edx: res.edx,
})
} else {
Expand All @@ -519,8 +519,8 @@ impl<R: CpuIdReader> CpuId<R> {
let res = self.read.cpuid1(EAX_STRUCTURED_EXTENDED_FEATURE_INFO);
Some(ExtendedFeatures {
_eax: res.eax,
ebx: ExtendedFeaturesEbx { bits: res.ebx },
ecx: ExtendedFeaturesEcx { bits: res.ecx },
ebx: ExtendedFeaturesEbx::from_bits_truncate(res.ebx),
ecx: ExtendedFeaturesEcx::from_bits_truncate(res.ecx),
_edx: res.edx,
})
} else {
Expand Down Expand Up @@ -550,7 +550,7 @@ impl<R: CpuIdReader> CpuId<R> {
let res = self.read.cpuid1(EAX_PERFORMANCE_MONITOR_INFO);
Some(PerformanceMonitoringInfo {
eax: res.eax,
ebx: PerformanceMonitoringFeaturesEbx { bits: res.ebx },
ebx: PerformanceMonitoringFeaturesEbx::from_bits_truncate(res.ebx),
_ecx: res.ecx,
edx: res.edx,
})
Expand Down Expand Up @@ -605,13 +605,13 @@ impl<R: CpuIdReader> CpuId<R> {
let res1 = self.read.cpuid2(EAX_EXTENDED_STATE_INFO, 1);
Some(ExtendedStateInfo {
read: self.read.clone(),
eax: ExtendedStateInfoXCR0Flags { bits: res.eax },
eax: ExtendedStateInfoXCR0Flags::from_bits_truncate(res.eax),
ebx: res.ebx,
ecx: res.ecx,
_edx: res.edx,
eax1: res1.eax,
ebx1: res1.ebx,
ecx1: ExtendedStateInfoXSSFlags { bits: res1.ecx },
ecx1: ExtendedStateInfoXSSFlags::from_bits_truncate(res1.ecx),
_edx1: res1.edx,
})
} else {
Expand Down Expand Up @@ -2431,6 +2431,8 @@ impl Debug for FeatureInfo {
}

bitflags! {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct FeatureInfoFlags: u64 {
// ECX flags

Expand Down Expand Up @@ -3682,6 +3684,8 @@ impl Debug for ExtendedFeatures {
}

bitflags! {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct ExtendedFeaturesEbx: u32 {
/// FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1. (Bit 00)
const FSGSBASE = 1 << 0;
Expand Down Expand Up @@ -3750,6 +3754,8 @@ bitflags! {
}

bitflags! {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct ExtendedFeaturesEcx: u32 {
/// Bit 0: Prefetch WT1. (Intel® Xeon Phi™ only).
const PREFETCHWT1 = 1 << 0;
Expand Down Expand Up @@ -3941,6 +3947,8 @@ impl Debug for PerformanceMonitoringInfo {
}

bitflags! {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct PerformanceMonitoringFeaturesEbx: u32 {
/// Core cycle event not available if 1. (Bit 0)
const CORE_CYC_EV_UNAVAILABLE = 1 << 0;
Expand Down Expand Up @@ -4097,6 +4105,8 @@ impl<R: CpuIdReader> Debug for ExtendedTopologyIter<R> {
}

bitflags! {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct ExtendedStateInfoXCR0Flags: u32 {
/// legacy x87 (Bit 00).
const LEGACY_X87 = 1 << 0;
Expand Down Expand Up @@ -4127,16 +4137,42 @@ bitflags! {

/// IA32_XSS HDC State (Bit 13).
const IA32_XSS_HDC = 1 << 13;

/// AMX TILECFG state (Bit 17)
const AMX_TILECFG = 1 << 17;

/// AMX TILEDATA state (Bit 17)
const AMX_TILEDATA = 1 << 18;
}
}

bitflags! {
#[repr(transparent)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
struct ExtendedStateInfoXSSFlags: u32 {
/// IA32_XSS PT (Trace Packet) State (Bit 08).
const PT = 1 << 8;

/// IA32_XSS PASID state (Bit 10)
const PASID = 1 << 10;

/// IA32_XSS CET user state (Bit 11)
const CET_USER = 1 << 11;

/// IA32_XSS CET supervisor state (Bit 12)
const CET_SUPERVISOR = 1 << 12;

/// IA32_XSS HDC State (Bit 13).
const HDC = 1 << 13;

/// IA32_XSS UINTR state (Bit 14)
const UINTR = 1 << 14;

/// IA32_XSS LBR state (Bit 15)
const LBR = 1 << 15;

/// IA32_XSS HWP state (Bit 16)
const HWP = 1 << 16;
}
}

Expand Down
24 changes: 11 additions & 13 deletions src/tests/i5_3337u.rs
View file
Expand Up @@ -16,9 +16,7 @@ fn feature_info() {
vendor: Vendor::Intel,
eax: 198313,
ebx: 34605056,
edx_ecx: FeatureInfoFlags {
bits: 2109399999 | 3219913727 << 32,
},
edx_ecx: FeatureInfoFlags::from_bits_truncate(2109399999 | 3219913727 << 32),
};

assert!(finfo.base_model_id() == 10);
Expand Down Expand Up @@ -177,9 +175,9 @@ fn monitor_mwait_features() {
#[test]
fn thermal_power_features() {
let tpfeatures = ThermalPowerInfo {
eax: ThermalPowerFeaturesEax { bits: 119 },
eax: ThermalPowerFeaturesEax::from_bits_truncate(119),
ebx: 2,
ecx: ThermalPowerFeaturesEcx { bits: 9 },
ecx: ThermalPowerFeaturesEcx::from_bits_truncate(9),
_edx: 0,
};

Expand Down Expand Up @@ -239,8 +237,8 @@ fn thermal_power_features() {
fn extended_features() {
let tpfeatures = ExtendedFeatures {
_eax: 0,
ebx: ExtendedFeaturesEbx { bits: 641 },
ecx: ExtendedFeaturesEcx { bits: 0 },
ebx: ExtendedFeaturesEbx::from_bits_truncate(641),
ecx: ExtendedFeaturesEcx::from_bits_truncate(0),
_edx: 0,
};
assert!(tpfeatures._eax == 0);
Expand Down Expand Up @@ -274,7 +272,7 @@ fn extended_features() {
| ExtendedFeaturesEbx::SMAP
| ExtendedFeaturesEbx::CLFLUSHOPT
| ExtendedFeaturesEbx::PROCESSOR_TRACE,
ecx: ExtendedFeaturesEcx { bits: 0 },
ecx: ExtendedFeaturesEcx::from_bits_truncate(0),
_edx: 201326592,
};

Expand Down Expand Up @@ -305,7 +303,7 @@ fn direct_cache_access_info() {
fn performance_monitoring_info() {
let pm = PerformanceMonitoringInfo {
eax: 120587267,
ebx: PerformanceMonitoringFeaturesEbx { bits: 0 },
ebx: PerformanceMonitoringFeaturesEbx::from_bits_truncate(0),
_ecx: 0,
edx: 1539,
};
Expand Down Expand Up @@ -402,13 +400,13 @@ fn extended_topology_info_v2() {
fn extended_state_info() {
let es = ExtendedStateInfo {
read: CpuIdReaderNative,
eax: ExtendedStateInfoXCR0Flags { bits: 7 },
eax: ExtendedStateInfoXCR0Flags::from_bits_truncate(7),
ebx: 832,
ecx: 832,
_edx: 0,
eax1: 1,
ebx1: 0,
ecx1: ExtendedStateInfoXSSFlags { bits: 0 },
ecx1: ExtendedStateInfoXSSFlags::from_bits_truncate(0),
_edx1: 0,
};

Expand Down Expand Up @@ -588,13 +586,13 @@ fn extended_state_info3() {
fn extended_state_info2() {
let es = ExtendedStateInfo {
read: CpuIdReaderNative,
eax: ExtendedStateInfoXCR0Flags { bits: 31 },
eax: ExtendedStateInfoXCR0Flags::from_bits_truncate(31),
ebx: 1088,
ecx: 1088,
_edx: 0,
eax1: 15,
ebx1: 960,
ecx1: ExtendedStateInfoXSSFlags { bits: 256 },
ecx1: ExtendedStateInfoXSSFlags::from_bits_truncate(256),
_edx1: 0,
};

Expand Down

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