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Implement secure boost scheme phase 2 - enable secure xgboost via processor interface #10124
base: vertical-federated-learning
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Implement secure boost scheme phase 2 - enable secure xgboost via processor interface #10124
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…ute under secure scenario
…valent to broadcast
…lobal best split, but need to further apply split correctly
…w histogram transmission data structure of a flat vector
Hi @trivialfis, this PR is ready for review, we have some remaining failed checks due to two issues: |
Processor windows support
Added support for horizontal secure XGBoost
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/*! \brief An processor interface to handle tasks that require external library through plugins */ | ||
class Processor { | ||
public: |
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Here is my understanding about these interfaces. Please confirm if it's correct:
ProcessGHPairs: active party encrypts g&h pairs
HandleGHPairs: passive parties save encrypted g&h pairs in local
ProcessAggregation: passive parties each cacluate it's histogram based on encrypted g&h pairs, the output is ciphertext
HandleAggregation: active party decrypts the allgathered historgram ciphertexts
ProcessHistograms: active party encrypted allgathered & decrypted histograms?
HandleHistograms: active parth decrypts the allgathered historgram ciphertexts?
I have two more questions:
- Where are ProcessHistograms and HandleHistograms needed in secure xgboost?
- Passive parties need a public key to perform HE addition calculations. The public key is generated by the active party. So I think there should be two more interfaces like ProcessPublicKey and HandlePublicKey.
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Hi @shaojian-ant , thanks for the question!
"ProcessHistograms" and "HandleHistograms" are for the upcoming secure horizontal scheme, I will remove these two from this PR to avoid confusion.
Under secure federated mode (see RFC #9987), the HE is supposed to be performed outside xgboost via the interface, hence the key management, etc. will not be part of xgboost lib (and hence in xgboost we only have a "mock" interface inplementation to illustrate the functionality)
Add extensions to the vertical pipeline implemented in phase 1 to call Processor interface at proper locations to enable secure features: