__   _ __      _______  ____
             / /  (_) /____ / __/ _ \/  _/
            / /__/ / __/ -_)\ \/ ___// /
           /____/_/\__/\__/___/_/  /___/

    Copyright (c) 2020-2022, LiteSPI Developers

[> Intro

LiteSPI provides a small footprint and configurable SPI core.

LiteSPI is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

Using Migen to describe the HDL allows the core to be highly and easily configurable.

LiteSPI can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core.

[> Features

PHY:

• Portable/Generic.
• Single/Dual/Quad/Octal SPI Bus support.
• Dynamic Clk frequency configuration and auto-calibration.

Core:

• Dynamic Crossbar.
• MMAP read accesses.
• CSR-based read/write accesses.

[> Getting started

Examples of integration can be found on various supported boards of LiteX-Boards repository.

[> Tests

Unit tests are available in ./test/. To run all the unit tests: ./setup.py test Tests can also be run individually: python3 -m unittest test.test_name

[> License

LiteSPI is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use LiteSPI for closed-source proprietary designs. Even though we do not require you to do so, those things are awesome, so please do them if possible:

• tell us that you are using LiteSPI
• cite LiteSPI in publications related to research it has helped
• send us feedback and suggestions for improvements
• send us bug reports when something goes wrong
• send us the modifications and improvements you have done to LiteSPI.