fixup! gdbstub_arch: Add support for AArch64

gdbstub_arch/src/aarch64/fpu.xml

@@ -121,7 +121,7 @@
          operations.  -->
     <field name="N" start="31" end="31"/>
   </flags>
-  <reg name="fpsr" bitsize="32" type="fpsr_flags" regnum="55841"/>
+  <reg name="fpsr" bitsize="32" type="fpsr_flags"/>
 
   <flags id="fpcr_flags" size="4">
     <!-- Flush Inputs to Zero (part of Armv8.7).  -->
@@ -156,5 +156,5 @@
     <!-- Alternative half-precision control bit.  -->
     <field name="AHP" start="26" end="26"/>
   </flags>
-  <reg name="fpcr" bitsize="32" type="fpcr_flags" regnum="55840"/>
+  <reg name="fpcr" bitsize="32" type="fpcr_flags"/>
 </feature>

gdbstub_arch/src/aarch64/reg/aarch64_core.rs

@@ -16,6 +16,12 @@ pub struct AArch64CoreRegs {
     pub pc: u64,
     /// Process State (GDB uses the AArch32 CPSR name)
     pub cpsr: u32,
+    /// FP & SIMD Registers (V0-V31)
+    pub v: [u128; 32],
+    /// Floating-point Control Register
+    pub fpcr: u32,
+    /// Floating-point Status Register
+    pub fpsr: u32,
 }
 
 impl Registers for AArch64CoreRegs {
@@ -40,16 +46,24 @@ impl Registers for AArch64CoreRegs {
         write_bytes!(self.sp);
         write_bytes!(self.pc);
         write_bytes!(self.cpsr);
+        for reg in self.v.iter() {
+            write_bytes!(reg);
+        }
+        write_bytes!(self.fpcr);
+        write_bytes!(self.fpsr);
     }
 
     fn gdb_deserialize(&mut self, bytes: &[u8]) -> Result<(), ()> {
-        const U64_END: usize = core::mem::size_of::<u64>() * 33;
+        const CPSR_OFF: usize = core::mem::size_of::<u64>() * 33;
+        const FPSIMD_OFF: usize = CPSR_OFF + core::mem::size_of::<u32>();
+        const FPCR_OFF: usize = FPSIMD_OFF + core::mem::size_of::<u128>() * 32;
+        const END: usize = FPCR_OFF + core::mem::size_of::<u32>() * 2;
 
-        if bytes.len() % core::mem::size_of::<u32>() != 0 {
+        if bytes.len() < END {
             return Err(());
         }
 
-        let mut regs = bytes[0..U64_END]
+        let mut regs = bytes[0..CPSR_OFF]
             .chunks_exact(core::mem::size_of::<u64>())
             .map(|c| u64::from_le_bytes(c.try_into().unwrap()));
 
@@ -59,12 +73,27 @@ impl Registers for AArch64CoreRegs {
         self.sp = regs.next().ok_or(())?;
         self.pc = regs.next().ok_or(())?;
 
-        let mut regs = bytes[U64_END..]
+        let mut regs = bytes[CPSR_OFF..FPSIMD_OFF]
             .chunks_exact(core::mem::size_of::<u32>())
             .map(|c| u32::from_le_bytes(c.try_into().unwrap()));
 
         self.cpsr = regs.next().ok_or(())?;
 
+        let mut regs = bytes[FPSIMD_OFF..FPCR_OFF]
+            .chunks_exact(core::mem::size_of::<u128>())
+            .map(|c| u128::from_le_bytes(c.try_into().unwrap()));
+
+        for reg in self.v.iter_mut() {
+            *reg = regs.next().ok_or(())?
+        }
+
+        let mut regs = bytes[FPCR_OFF..]
+            .chunks_exact(core::mem::size_of::<u32>())
+            .map(|c| u32::from_le_bytes(c.try_into().unwrap()));
+
+        self.fpcr = regs.next().ok_or(())?;
+        self.fpsr = regs.next().ok_or(())?;
+
         Ok(())
     }
 }

gdbstub_arch/src/aarch64/reg/id.rs

@@ -54,6 +54,8 @@ impl RegId for AArch64RegId {
             32 => Self::Pc,
             33 => Self::Pstate,
             34..=65 => Self::V((id - 34) as u8),
+            66 => Self::FPSR,
+            67 => Self::FPCR,
             #[allow(clippy::unusual_byte_groupings)]
             // We configure GDB to use regnums that correspond to the architectural u16 opcode
             // and avoid clashes with core registers thanks to op0==0b00 and op0==0b01 not being