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Add (partial) support for RISC-V (#21)
* implement Arch for RISC-V 32/64 Introduces support for **integer** RISC-V ISA. * fix minor style issues in the riscv module
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pub mod arm; | ||
pub mod mips; | ||
pub mod msp430; | ||
pub mod riscv; | ||
mod traits; | ||
pub mod x86; | ||
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//! Support for the [RISC-V](https://riscv.org/) architecture. | ||
//! | ||
//! *Note*: currently only supports integer versions of the ISA. | ||
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use crate::arch::Arch; | ||
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pub mod reg; | ||
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/// Implements `Arch` for 32-bit RISC-V. | ||
#[derive(Eq, PartialEq)] | ||
pub struct Riscv32; | ||
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/// Implements `Arch` for 64-bit RISC-V. | ||
#[derive(Eq, PartialEq)] | ||
pub struct Riscv64; | ||
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impl Arch for Riscv32 { | ||
type Usize = u32; | ||
type Registers = reg::RiscvCoreRegs<u32>; | ||
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fn target_description_xml() -> Option<&'static str> { | ||
Some(r#"<target version="1.0"><architecture>riscv</architecture></target>"#) | ||
} | ||
} | ||
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impl Arch for Riscv64 { | ||
type Usize = u64; | ||
type Registers = reg::RiscvCoreRegs<u64>; | ||
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fn target_description_xml() -> Option<&'static str> { | ||
Some(r#"<target version="1.0"><architecture>riscv64</architecture></target>"#) | ||
} | ||
} |
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//! `GdbRegister` structs for RISC-V architectures. | ||
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mod riscv; | ||
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pub use riscv::RiscvCoreRegs; |
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use crate::arch::Registers; | ||
use crate::internal::LeBytes; | ||
use num_traits::PrimInt; | ||
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/// RISC-V Integer registers. | ||
/// | ||
/// The register width is set to `u32` or `u64` based on the `<U>` type. | ||
/// | ||
/// Useful links: | ||
/// * [GNU binutils-gdb XML descriptions](https://github.com/bminor/binutils-gdb/blob/master/gdb/features/riscv) | ||
/// * [riscv-tdep.h](https://github.com/bminor/binutils-gdb/blob/master/gdb/riscv-tdep.h) | ||
#[derive(Default)] | ||
pub struct RiscvCoreRegs<U> { | ||
/// General purpose registers (x0-x31) | ||
pub x: [U; 32], | ||
/// Program counter | ||
pub pc: U, | ||
} | ||
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impl<U> Registers for RiscvCoreRegs<U> | ||
where | ||
U: PrimInt + LeBytes + Default, | ||
{ | ||
fn gdb_serialize(&self, mut write_byte: impl FnMut(Option<u8>)) { | ||
macro_rules! write_le_bytes { | ||
($value:expr) => { | ||
let mut buf = [0; 16]; | ||
// infallible (unless digit is a >128 bit number) | ||
let len = $value.to_le_bytes(&mut buf).unwrap(); | ||
let buf = &buf[..len]; | ||
for b in buf { | ||
write_byte(Some(*b)); | ||
} | ||
}; | ||
} | ||
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// Write GPRs | ||
for reg in self.x.iter() { | ||
write_le_bytes!(reg); | ||
} | ||
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// Program Counter is regnum 33 | ||
write_le_bytes!(&self.pc); | ||
} | ||
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fn gdb_deserialize(&mut self, bytes: &[u8]) -> Result<(), ()> { | ||
let ptrsize = core::mem::size_of::<U>(); | ||
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// ensure bytes.chunks_exact(ptrsize) won't panic | ||
if bytes.len() % ptrsize != 0 { | ||
return Err(()); | ||
} | ||
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let mut regs = bytes | ||
.chunks_exact(ptrsize) | ||
.map(|c| U::from_le_bytes(c).unwrap()); | ||
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// Read GPRs | ||
for reg in self.x.iter_mut() { | ||
*reg = regs.next().ok_or(())? | ||
} | ||
self.pc = regs.next().ok_or(())?; | ||
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if regs.next().is_some() { | ||
return Err(()); | ||
} | ||
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Ok(()) | ||
} | ||
} |