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Verilog-CPU
Verilog-CPU PublicIn this project, simple CPU are implemented in verilog. To be specific, project 5 is for single cycle CPU, project 6 is for pipeline CPU.
Verilog 1
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Text-Detection-and-Translation-System
Text-Detection-and-Translation-System PublicIn this project, the text will be detected from the images, then it will be translated into targeted language, here, we make it Chinese.
Makefile
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