Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merge pull request #46 from christian-lanius/escaped_character_fix
allow backslash in string, fixes issue #45
- Loading branch information
Showing
3 changed files
with
33 additions
and
1 deletion.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,16 @@ | ||
(DELAYFILE | ||
(SDFVERSION "3.0") | ||
(TIMESCALE 1ps) | ||
|
||
(CELL | ||
(CELLTYPE "vpr_interconnect") | ||
(INSTANCE dut/routing_segment_b0_output_0_0_to_c0_input_0_0) | ||
(DELAY | ||
(ABSOLUTE | ||
(INTERCONNECT clk_i TESTENV/clock_generator/clk_mux/CLK1 (1.4:8.4:8.4)(1.6:7.7:7.7)) | ||
(INTERCONNECT rstn_i TESTENV/reset_synchronizer_genblk1\[0\]\.ff_1_reg/RESET (3.7:3.5:3.5)(3.8:3.5:3.5)) | ||
(INTERCONNECT rstn_i TESTENV/reset_synchronizer_genblk1\[0\]\.ff_2_reg/RESET (3.7:3.5:3.5)(3.8:3.5:3.5)) | ||
) | ||
) | ||
) | ||
) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,16 @@ | ||
(DELAYFILE | ||
(SDFVERSION "3.0") | ||
(TIMESCALE 1ps) | ||
|
||
(CELL | ||
(CELLTYPE "vpr_interconnect") | ||
(INSTANCE dut/routing_segment_b0_output_0_0_to_c0_input_0_0) | ||
(DELAY | ||
(ABSOLUTE | ||
(INTERCONNECT clk_i TESTENV/clock_generator/clk_mux/CLK1 (1.4:8.4:8.4)(1.6:7.7:7.7)) | ||
(INTERCONNECT rstn_i TESTENV/reset_synchronizer_genblk1\[0\]\.ff_1_reg/RESET (3.7:3.5:3.5)(3.8:3.5:3.5)) | ||
(INTERCONNECT rstn_i TESTENV/reset_synchronizer_genblk1\[0\]\.ff_2_reg/RESET (3.7:3.5:3.5)(3.8:3.5:3.5)) | ||
) | ||
) | ||
) | ||
) |