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winch(aarch64): Use single precision fmov (#8460)
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* winch: Use single precision fmov

This commit is a follow-up to #8365. In #8453 single precision fmov was introduced in Cranelift, so now we can make use that instruction in Winch.

* Remove stale `TODO` comment
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@saulecabrera
saulecabrera committed Apr 24, 2024
1 parent 1f8c3df commit a54d34f
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Showing 20 changed files with 38 additions and 29 deletions.
2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_add/const.wat
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Expand Up @@ -24,7 +24,7 @@
;; movk w16, #0x3f8c, lsl #16
;; fmov s1, w16
;; fadd s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x10
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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4 changes: 2 additions & 2 deletions tests/disas/winch/aarch64/f32_add/locals.wat
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Expand Up @@ -39,8 +39,8 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fadd s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
;; ret
;; ret
4 changes: 2 additions & 2 deletions tests/disas/winch/aarch64/f32_add/params.wat
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Expand Up @@ -22,8 +22,8 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fadd s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
;; ret
;; ret
2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_div/const.wat
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Expand Up @@ -24,7 +24,7 @@
;; movk w16, #0x3f8c, lsl #16
;; fmov s1, w16
;; fdiv s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x10
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_div/locals.wat
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Expand Up @@ -39,7 +39,7 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fdiv s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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4 changes: 2 additions & 2 deletions tests/disas/winch/aarch64/f32_div/params.wat
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Expand Up @@ -22,8 +22,8 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fdiv s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
;; ret
;; ret
2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_max/const.wat
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Expand Up @@ -24,7 +24,7 @@
;; movk w16, #0x3f8c, lsl #16
;; fmov s1, w16
;; fmax s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x10
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_max/locals.wat
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Expand Up @@ -39,7 +39,7 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fmax s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_max/params.wat
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Expand Up @@ -22,7 +22,7 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fmax s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_min/const.wat
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Expand Up @@ -24,7 +24,7 @@
;; movk w16, #0x3f8c, lsl #16
;; fmov s1, w16
;; fmin s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x10
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_min/locals.wat
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Expand Up @@ -39,7 +39,7 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fmin s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_min/params.wat
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Expand Up @@ -22,7 +22,7 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fmin s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_mul/const.wat
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Expand Up @@ -24,7 +24,7 @@
;; movk w16, #0x3f8c, lsl #16
;; fmov s1, w16
;; fmul s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x10
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_mul/locals.wat
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Expand Up @@ -39,7 +39,7 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fmul s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_mul/params.wat
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Expand Up @@ -22,7 +22,7 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fmul s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_sub/const.wat
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Expand Up @@ -24,7 +24,7 @@
;; movk w16, #0x3f8c, lsl #16
;; fmov s1, w16
;; fsub s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x10
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_sub/locals.wat
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Expand Up @@ -39,7 +39,7 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fsub s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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2 changes: 1 addition & 1 deletion tests/disas/winch/aarch64/f32_sub/params.wat
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Expand Up @@ -22,7 +22,7 @@
;; ldur w0, [x28]
;; ldur w1, [x28, #4]
;; fsub s1, s1, s0
;; fmov d0, d1
;; fmov s0, s1
;; add sp, sp, #0x18
;; mov x28, sp
;; ldp x29, x30, [sp], #0x10
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22 changes: 16 additions & 6 deletions winch/codegen/src/isa/aarch64/asm.rs
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Expand Up @@ -161,12 +161,22 @@ impl Assembler {
});
}

pub fn fmov64_rr(&mut self, rm: Reg, rd: Reg) {
let writable_rd = Writable::from_reg(rd.into());
self.emit(Inst::FpuMove64 {
rd: writable_rd,
rn: rm.into(),
})
/// Floating point register to register move.
pub fn fmov_rr(&mut self, rn: Reg, rd: Reg, size: OperandSize) {
let writable = Writable::from_reg(rd.into());
let inst = match size {
OperandSize::S32 => Inst::FpuMove32 {
rd: writable,
rn: rn.into(),
},
OperandSize::S64 => Inst::FpuMove64 {
rd: writable,
rn: rn.into(),
},
_ => unreachable!(),
};

self.emit(inst);
}

pub fn mov_to_fpu(&mut self, rn: Reg, rd: Reg, size: OperandSize) {
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3 changes: 1 addition & 2 deletions winch/codegen/src/isa/aarch64/masm.rs
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Expand Up @@ -212,8 +212,7 @@ impl Masm for MacroAssembler {
}
(RegImm::Reg(rs), rd) => match (rs.class(), rd.class()) {
(RegClass::Int, RegClass::Int) => self.asm.mov_rr(rs, rd, size),
// TODO: verify whether we should use `fmov sd, sn` for F32.
(RegClass::Float, RegClass::Float) => self.asm.fmov64_rr(rs, rd),
(RegClass::Float, RegClass::Float) => self.asm.fmov_rr(rs, rd, size),
(RegClass::Int, RegClass::Float) => self.asm.mov_to_fpu(rs, rd, size),
_ => todo!(),
},
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