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395 Open 1,263 Closed
395 Open 1,263 Closed
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Issues list

CXXRTL: >20x compile time regression with clang++-18 bug cxxrtl pending-verification This issue is pending verification and/or reproduction
#4419 opened May 27, 2024 by Wren6991
1
A topological loop is generated after using async2sync pending-verification This issue is pending verification and/or reproduction
#4414 opened May 24, 2024 by ZhiyuanYan
2
Yosys right shift error pending-verification This issue is pending verification and/or reproduction
#4413 opened May 24, 2024 by WeneneW
create a pip install package wheel for Windows feature-request
#4410 opened May 22, 2024 by eabase
3
Abnormal output pending-verification This issue is pending verification and/or reproduction
#4407 opened May 22, 2024 by WeneneW
make error 'abc' is not configured as a git submodule. pending-verification This issue is pending verification and/or reproduction
#4403 opened May 20, 2024 by Krishnakumarmohanraj
5
read_verilog doesn't respect signed keyword bug
#4402 opened May 18, 2024 by WeneneW
2
Yosys seems to handle bit operations on empty strings inconsistently with the original design. bug
#4395 opened May 13, 2024 by WeneneW
4
Wired-or (wor) wires generate $or / $reduce_or cells in output bug
#4389 opened May 10, 2024 by jswrightoc
3
No bad property in btor2 file generated from verilog (write_btor should error for $check cells) error handling Error handling and reporting
#4381 opened May 8, 2024 by gipsyh
3
Add support for SystemVerilog's ==? and !=? operators feature-request
#4374 opened May 4, 2024 by jmi2k
Inout can't be read with constant value feature-request
#4370 opened May 3, 2024 by alchitry
3
Spurious warnings "select out of bounds on signal" when there is no such thing ... bug
#4363 opened Apr 29, 2024 by smunaut
1
write_smt2: "-wires" option leads to inequivalent descriptions pending-verification This issue is pending verification and/or reproduction
#4361 opened Apr 27, 2024 by YikeZhou
opt: no "-purge" option but public names removed bug
#4357 opened Apr 25, 2024 by YikeZhou
2
Should -nomx8 be the default for the GateMate? pending-verification This issue is pending verification and/or reproduction
#4355 opened Apr 23, 2024 by spth
Crash in yosys-abc pending-verification This issue is pending verification and/or reproduction
#4352 opened Apr 22, 2024 by maliberty
"ERROR: Assert `count_id(wire->name) == 0' failed in kernel/rtlil.cc:2143" when using synth_{ice40,ecp5} on simple design bug
#4349 opened Apr 20, 2024 by cr1901
@Ravenslofty
3
synth_* passes should call check -mapped
#4348 opened Apr 20, 2024 by nakengelhardt
Another out-of-memory problem with for loop pending-verification This issue is pending verification and/or reproduction
#4345 opened Apr 19, 2024 by YikeZhou
Assertion Failure in AST Processing: node->bits == v at frontends/ast/ast.cc:855 pending-verification This issue is pending verification and/or reproduction
#4335 opened Apr 14, 2024 by 1353369570
Latch inferred for x signal bug
#4325 opened Apr 8, 2024 by spth
4
Reduce default severity of Verific messages that produce warnings on commonly used coding styles
#4324 opened Apr 8, 2024 by nakengelhardt
Parameters in other packages SystemVerilog Issues and questions related to SystemVerilog wontfix
#4318 opened Apr 4, 2024 by pentin-as
2
Assertion Failure in genrtlil.cc When Handling Signedness Issue Description: pending-verification This issue is pending verification and/or reproduction
#4307 opened Apr 1, 2024 by 1353369570
1
ProTip! Updated in the last three days: updated:>2024-05-26.