PhD researcher, Member of the Electronic Circuits, Systems and Applications (@ECSAlab) Laboratory
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4bitCounterParLoad
4bitCounterParLoad PublicA 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder
VHDL 1
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FSM_CarAlarm
FSM_CarAlarm PublicFinite-State Machine Design of a Simple Car Security Alarm on FPGA
VHDL 3
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CastaliaGCF
CastaliaGCF PublicRouting Algorithm for Mobile Agent (MA) based Wireless Sensor Network (WSN) on Castalia Simulator
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