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34 Open 44 Closed
34 Open 44 Closed
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Issues list

PandABrick encoders
#184 opened Mar 14, 2024 by tomtrafford
Investigate using SI5338 for MGT clocking on PandABrick
#180 opened Mar 1, 2024 by glennchid
4
PCAP.TS_START not zeroed when GATE already high at the start of capture bug
#179 opened Feb 29, 2024 by coretl
@tomtrafford
3
Send timestamp over SFP via PandA sync enhancement
#175 opened Feb 15, 2024 by coretl
Support for ML model deployment
#166 opened Nov 3, 2023 by marcelldls
2
The us_system block should be defined as a "pure" extension block without any VHDL implementation
#165 opened Nov 1, 2023 by Araneidae
Remove component declarations from VHDL source
#161 opened Sep 21, 2023 by Araneidae
EVR: Implement event forwarding on EVR TX
#159 opened Sep 20, 2023 by glennchid
EVR: Vary MGT refclk frquency
#158 opened Sep 20, 2023 by glennchid
Add version number to created devicetree
#154 opened Sep 20, 2023 by tomtrafford
Populate clock_target and clock_actual
#150 opened Sep 11, 2023 by tomtrafford
PandABrick: remove all test code and tidy top level
#149 opened Sep 8, 2023 by glennchid
PandABrick: DCARD mode
#148 opened Sep 8, 2023 by glennchid
PandABrick: tidy up sfp_pand_sync
#147 opened Sep 8, 2023 by glennchid
1
PandABrick: convert verilog file to VHDL
#146 opened Sep 8, 2023 by glennchid
PandABrick: LEDs and I2C
#145 opened Sep 8, 2023 by glennchid
PandABrick: tidy up encoders module
#144 opened Sep 8, 2023 by glennchid
Voltage i2c readings do not work from cold restart
#141 opened Aug 23, 2023 by tomtrafford
1
Modify build system to allow SFP connections through the FMC interface
#136 opened Jul 12, 2023 by tomtrafford
@glennchid @tomtrafford
1
Investigate Dynamic Function Exchange
#135 opened Jun 28, 2023 by tomtrafford
Consider the use of HOG
#134 opened Jun 26, 2023 by coretl
Remove unused/bogus resets
#133 opened Jun 23, 2023 by glennchid
@glennchid
Support the CAENels FMC-Pico-1M4
#125 opened Apr 21, 2023 by coretl
4
Make A and B outputs on INENC block only update when used
#123 opened Apr 19, 2023 by tomtrafford
Change verilog test-bench to VHDL and investigate running tests in ghdl
#122 opened Apr 19, 2023 by glennchid
@glennchid
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