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riscv64gcv.S -> riscv_rva23u64.S
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With QEMU v8.2 the test command is now:

    for VLEN in 128 256 512 1024 ; do
        CC="$HOME/llvm-project/build/bin/clang" CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_LINKER=riscv64-linux-gnu-gcc CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUSTFLAGS="-L /usr/lib/gcc/riscv64-linux-gnu/12.2.0" CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUNNER="$HOME/qemu/build/qemu-riscv64 -L /usr/riscv64-linux-gnu -cpu rv64,v=true,vext_spec=v1.0,vlen=$VLEN,zbb=true,zvbb=true" cargo test --target riscv64gc-unknown-linux-gnu
    done
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oconnor663 committed Dec 23, 2023
1 parent f7b4c2b commit 3ddab49
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Showing 2 changed files with 9 additions and 6 deletions.
2 changes: 1 addition & 1 deletion rust/guts/build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -232,7 +232,7 @@ fn build_neon_c_intrinsics() {
fn build_riscv64gcv_assembly() {
println!("cargo:rustc-cfg=blake3_riscv64gcv_ffi");
let mut build = new_build();
let asm_path = "src/riscv64gcv.S";
let asm_path = "src/riscv_rva23u64.S";
build.file(asm_path);
build.flag("--target=riscv64");
build.flag("-march=rv64gcv_zbb_zvbb1p0");
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13 changes: 8 additions & 5 deletions rust/guts/src/riscv64gcv.S → rust/guts/src/riscv_rva23u64.S
Original file line number Diff line number Diff line change
@@ -1,8 +1,11 @@
// This implementation currently assumes riscv64gcv_zbb_zvbb. Zvbb in particular ("Vector
// Bit-manipulation used in Cryptography") is a bleeding-edge extension that was only frozen a few
// weeks ago at the time I'm writing this comment. Compiling and testing this code currently
// requires quite a lot of effort, including building Clang from master and building QEMU from a
// custom branch. Please don't expect this code to be usable on real hardware for some time.
// This implementation targets the RVA23 profile, particularly V, Zvbb, and
// Zbb, that is the vector extension and the bit-manipulation extensions. As of
// December 2023, most real-world hardware does *not* support these extensions.
// This implementation also assumes that misaligned vector loads and stores are
// supported, in particular for the vlsseg8e32.v and vssseg8e32.v instructions.
//
// Compiling and testing this code requires very recent versions of Clang (v17)
// and QEMU (v8.2).

#define IV0 0x6A09E667
#define IV1 0xBB67AE85
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