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The repository hosts an ongoing project dedicated to the development of an implementation for the Advanced Encryption Standard (AES) 128-bit block cipher in UART communication. Please be advised that this project is currently in progress and subject to updates.
A low power microprocessor
Updated
Jun 2, 2024
Verilog
Verilator open-source SystemVerilog simulator and lint system
Sol-1: A CPU/Computer System made from 74 series logic.
Basic implementation of SDRAM controller for De0-nano board.
Updated
Jun 2, 2024
Verilog
A package to generate Verilog/SystemVerilog code on Julia.
Updated
Jun 2, 2024
Julia
Structural Netlist API (and more) for EDA post synthesis flow development
Scripts to build and use docker images including GHDL
Updated
Jun 2, 2024
Shell
A C++ to Verilog translation tool with some basic guarantees that your code will work.
Very small and high performance CPU
Updated
Jun 2, 2024
Verilog
a verilog implementation of arbitrary waveform generator with Red Pitaya
Updated
Jun 2, 2024
Jupyter Notebook
learn the combinational and sequential logic circuit.
Updated
Jun 2, 2024
SystemVerilog
SystemVerilog compiler and language services
Norsk Data ND-120 CPU Design Documents. Modern Logisim and HDL implementation
Updated
Jun 1, 2024
Verilog
lists of most popular repositories for most My favoured programming languages
Updated
Jun 1, 2024
Python
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
Updated
Jun 1, 2024
Verilog
Hardware Design/Visualization/Simulation/RTLGeneration Framework
Updated
Jun 1, 2024
Jupyter Notebook
Updated
Jun 2, 2024
Verilog
TinyTapeout submission with the AY-3-8913 a 3-voice programmable sound generator (PSG) chip from General Instruments.
Updated
Jun 1, 2024
Python
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