VSDMemSOC Implementation flow:: RTL2GDSII
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Updated
Mar 1, 2024 - Verilog
VSDMemSOC Implementation flow:: RTL2GDSII
Final project at San Jose State University
This repository is my entry into scripting using TCL and an attempt to understand it's nuances in physical design flow in VLSI
Testcase generator and visualizer and verification for your 2019 CAD Contest Problem E
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
This repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I gathered in the lectures and the outcomes of my lab module.
Source files for the labs of the Microelectronic Systems course
SerDes RTL design, verification using UVM and Physical design.
Contains the all the assignments of CMOS ASIC Design Lab
Physical Design (2020 Spring)
This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI System Design Corporation. This workshop helped me gain hands-on experience with tools that are used in the physical design flow.
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
Design, layout, and simulation files of the paper "Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)-2×1 Surface" by M. Walter, J. Croshaw, S. S. H. Ng, K. Walus, R. Wolkow, and R. Wille in DATE 2024.
generic NetList data structure for VLSI
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
MNT Bench - An MNT tool for Benchmarking FCN circuits
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
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