Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
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Updated
Jun 11, 2022 - C++
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
32-bit Superscalar RISC-V CPU
Advanced Architecture Labs with CVA6
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
🎞 Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.
Super scalar Processor design
Kite: Architecture Simulator for RISC-V Instruction Set
A branch predictor simulator in C++ that tests 6 different types of branch predictors.
System benchmarks over JVM with JMH - SIMD (superscalar processing), Branch prediction, False sharing.
Computer Architecture UIUC SP 2018
Tool for visualizing and comparing different dynamic branch prediction methods for a pipelined processor.
Branch Predictor is a C# program that runs a gshare branch prediction simulation, according to a specified number of Global Buffer Table (GBT) and Global History Record (GHR) bits. 2019.
Implementation of the nine variations of the two-level algorithm for dynamic prediction deviations using the PIN tool
ECE552: Computer Architecture — Fall 2020.
A superscalar out-of‐order architectural simulator (With Memory Hierarchy).
CSCI 564 Advanced Computer Architecture Project 3 Description and Starter Code
MIPT-V Pipeline Flowchart Visualizer
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