Theseus on aarch64 - tracking issue

[NathanRoyer]

This is a tracking issue for the support of the aarch64/ARMv8 platform for Theseus.

bootstrap and basic initialization

• nano_core as an UEFI application
• log-compatible logger setup

memory management

• Configuring the TCR register
• porting the memory subsystem to aarch64 [WiP]
  • memory_structs, frame_allocator, page_allocator:
    Basic page_allocator and frame_allocator init for aarch64 #693
  • pte_flags:
    Architecture-dependent Page Table Entry (PTE) flags for x86_64 and aarch64 #699
  • memory_aarch64, page_table_entry, memory:
    Porting memory to aarch64 #701

interrupts

• Installing handlers
• Configuring GIC registers [WiP]
• Configuring the DAIF register
• porting Theseus' interrupt crates to aarch64
  • irq_safety
  • interrupts: Timer, GIC, IRQ support for aarch64 #727
  • architecture-independent interrupt handler: Use interrupt_controller in interrupts::aarch64 #972

task management

• Pre-requisite: figure out how to get core ID for each CPU
• context_switch_regular: Context Switching Primitives for AArch64 #744
• Basic Context type
• Determine register to use for passing a new task's ID
  • see context_switch_regular::ContextRegular::set_first_register()
  • i.e., from setup_context_trampoline to task_wrapper
• Configure aarch64 register used for Thread-Local storage
  • equivalent to FS_BASE and fs on x86_64; see Task::set_as_current_task()

SMP multicore support

• Detecting secondary cores
• Starting secondary cores at a controlled entry point
• Obtain current CPU ID; see get_my_apic_id()
• Configure paging / set up page tables for each CPU
• Enable interrupts and set up interrupt handlers on each CPU
  • Theseus shares one page table and one IDT across all CPUs on x86_64; this should also work on aarch64

Basic I/O support for interactivity

• Output over serial/UART
• Input over serial/UART
• Integration with device_manager and console
• Move PL011 crate to the main workspace: Move the PL011 driver into the main workspace #1040
• Move interrupts::PL011_RX_SPI to the board config crate

Loading and Linking

• Support aarch64 relocation types in write_relocation
  • Currently even the large code model on aarch64 does not generate branch instructions call/jump that can address the entire address space (as it does on x86_64).
  • Workaround: allocate pages for .text sections within a certain 128MiB range; see page allocator: support allocating pages within an address range #970.
  • Implement standard aarch64 relocation types for large code model and static relocations.
  • Finish implementing overflow checks for relocations.

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Future endeavors

Once the above core subsystems and components are finished, we will open separate issues for the following:

• Supporting unwinding via aarch64-specific trampolines in unwind

• Support basic PCI device discovery
  • kernel/pci currently assumes an x86-style interface using Port I/O to access PCI config data, but aarch64 uses MMIO.
  • Use MMIO mechanism to access PCI [extended] config space on x86_64 #1058

• More complex I/O, e.g., USB (?)
• Two-part abstraction of interrupt/CPU controllers:
  • per-CPU interrupt controller abstraction: enabling/disabling local timer interrupt, sending IPIs
  • system-wide interrupt controller abstraction: registering interrupt handlers, etc
• exceptions_full equivalent on aarch64