From b4598fb79ea005ed4207809e36cf7be4fc17d6e1 Mon Sep 17 00:00:00 2001 From: sakridge Date: Mon, 17 Jan 2022 09:37:05 -0800 Subject: [PATCH] Use VecDeque instead of Vec in sigverify stage (#22538) avoid bad performance of remove(0) for a single sender (cherry picked from commit 49443406fd729c5818ecf58ae773592804d35d89) # Conflicts: # core/src/sigverify_stage.rs --- core/benches/sigverify_stage.rs | 16 +++++++++++++--- core/src/sigverify_stage.rs | 10 +++++----- 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/core/benches/sigverify_stage.rs b/core/benches/sigverify_stage.rs index 6755db61eb9b02..7ea7cb4b37c0e8 100644 --- a/core/benches/sigverify_stage.rs +++ b/core/benches/sigverify_stage.rs @@ -1,4 +1,5 @@ #![feature(test)] +#![allow(clippy::integer_arithmetic)] extern crate solana_core; extern crate test; @@ -22,8 +23,7 @@ use { test::Bencher, }; -#[bench] -fn bench_packet_discard(bencher: &mut Bencher) { +fn run_bench_packet_discard(num_ips: usize, bencher: &mut Bencher) { solana_logger::setup(); let len = 30 * 1000; let chunk_size = 1024; @@ -32,7 +32,7 @@ fn bench_packet_discard(bencher: &mut Bencher) { let mut total = 0; - let ips: Vec<_> = (0..10_000) + let ips: Vec<_> = (0..num_ips) .into_iter() .map(|_| { let mut addr = [0u16; 8]; @@ -60,6 +60,16 @@ fn bench_packet_discard(bencher: &mut Bencher) { }); } +#[bench] +fn bench_packet_discard_many_senders(bencher: &mut Bencher) { + run_bench_packet_discard(1000, bencher); +} + +#[bench] +fn bench_packet_discard_single_sender(bencher: &mut Bencher) { + run_bench_packet_discard(1, bencher); +} + #[bench] fn bench_sigverify_stage(bencher: &mut Bencher) { solana_logger::setup(); diff --git a/core/src/sigverify_stage.rs b/core/src/sigverify_stage.rs index 62f190de8a77f4..33bf468eb09c69 100644 --- a/core/src/sigverify_stage.rs +++ b/core/src/sigverify_stage.rs @@ -13,7 +13,7 @@ use { solana_sdk::timing, solana_streamer::streamer::{self, PacketBatchReceiver, StreamerError}, std::{ - collections::HashMap, + collections::{HashMap, VecDeque}, sync::mpsc::{Receiver, RecvTimeoutError}, thread::{self, Builder, JoinHandle}, time::Instant, @@ -145,17 +145,17 @@ impl SigVerifyStage { for (packet_index, packets) in batch.packets.iter().enumerate() { let e = received_ips .entry(packets.meta.addr().ip()) - .or_insert_with(Vec::new); - e.push((batch_index, packet_index)); + .or_insert_with(VecDeque::new); + e.push_back((batch_index, packet_index)); } } let mut batch_len = 0; while batch_len < max_packets { for (_ip, indexes) in received_ips.iter_mut() { if !indexes.is_empty() { - indexes.remove(0); + indexes.pop_front(); batch_len += 1; - if batch_len >= MAX_SIGVERIFY_BATCH { + if batch_len >= max_packets { break; } }