spi: specify expectations regarding peripheral state between transactions

[Artur-Romaniuk]

Currently, SPI device traits deal with a transaction concept, which implies transmission of some data, while the CS is set for the whole duration. There is currently no guidance on how should the peripheral behave between transactions.

Issue

Certain SPI devices require bus synchronization, which means that the bus must not be disabled for the entire communication sequence and all lines must be kept in a known state (especially CLK). Communications sequence spans multiple SPI transactions.

Cause

Some HAL implementations disable SPI after each transaction, some don't. Some do it only after DMA transaction, some do it after each transaction. This unpredictable behavior of bus lanes, prevents a creation of generic device drivers that require synchronization.

Proposed solution

Embedded-hal should allow for specifying certain expectations regarding SPI bus state, to allow for correct behavior of device drivers for different HAL implementations.

[Dirbaio]

Certain SPI devices require bus synchronization, which means that the bus must not be disabled for the entire communication sequence and all lines must be kept in a known state (especially CLK). Communications sequence spans multiple SPI transactions.

can you share examples of chips requiring this?

[Artur-Romaniuk]

E.g. Qualcomm QCA7000 series chips