-
Notifications
You must be signed in to change notification settings - Fork 28
/
tristan-unified-access-page.html
607 lines (605 loc) · 16.5 KB
/
tristan-unified-access-page.html
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<style>
img {
max-width: 100%;
height: auto;
}
/* Add some spacing and border to the table */
table {
width: 100%;
border-collapse: collapse;
margin: 25px 0;
font-size: 0.9em;
font-family: sans-serif;
min-width: 400px;
box-shadow: 0 0 20px rgba(0, 0, 0, 0.15);
}
/* Style the table header */
thead tr {
background-color: #009879;
color: #ffffff;
text-align: left;
}
/* Style the table cells */
th, td {
padding: 12px 15px;
}
/* Style the table body rows with alternating colors */
tbody tr {
border-bottom: 1px solid #dddddd;
}
tbody tr:nth-of-type(even) {
background-color: #f3f3f3;
}
tbody tr:last-of-type {
border-bottom: 2px solid #009879;
}
/* Style for table body cells on hover */
tbody tr:hover {
background-color: #f1f1f1;
}
</style>
</head>
<body>
<h1 id="tristan-unified-access-page">Tristan Unified Access Page</h1>
<p>It provides references and descriptions of all the <a href="https://tristan-project.eu/">TRISTAN</a> IPs (hardware and software).
It serves as a <code>Virtual Repository</code> page, gathering all the information about the TRISTAN repositories, their status,
and the TRISTAN partners involved in them.
The Tristan Unified Access Page acts like a static page, to provide a single access point to all the repositories TRISTAN
contributes to. The updates and contributions will be upstreamed in the repository themselves.</p>
<p>Some of the repositories are hosted on the OpenHW Group GitHub forge, some are located on other public pages, and some are closed-source.
The diagram below shows how the TRISTAN repositories are organized.</p>
<img src="images/tristan_virtual_repo.png" style="max-width: 75%; height: auto;" align="center" />
<p>The Tristan Unified Access Page is the deliverable of the Task 2 of the Work Package 7 (7.2).</p>
<h2 id="tristan-ips">TRISTAN IPs</h2>
<h3 id="cores">CORES</h3>
<table>
<thead>
<tr>
<th>Repository</th>
<th>URL/Instructions</th>
<th>TRISTAN Working Items</th>
<th>Partners</th>
<th>Status</th>
<th>Description</th>
<th>License</th>
</tr>
</thead>
<tbody><tr>
<td>CVE2</td>
<td><a href="https://github.com/openhwgroup/cve2">CVE2</a></td>
<td>WI2.2.5, WI2.2.8, WI2.5.8</td>
<td>NXP, Synthara, Politecnico di Torino</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>Extensions to the micro-architecture of CV32E40P core</td>
<td><a href="https://github.com/pulp-platform/cv32e40p">CV32E40P (fork)</a></td>
<td>WI2.3.3</td>
<td>UNIBO</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>VSRV1: simple 32-bit Linux RISC-V</td>
<td>To Be Done</td>
<td>WI2.3.5</td>
<td>VLSI Solution</td>
<td>Design and Verification in progress</td>
<td></td>
<td>To Be Decided</td>
</tr>
<tr>
<td>CVA6</td>
<td><a href="https://github.com/openhwgroup/cva6">CVA6</a></td>
<td>WI2.4.1, WI2.4.2, WI2.4.3, WI2.4.5</td>
<td>Thales, Sysgo, TU Darmstadt, Bosch</td>
<td>Design and Verification in progress</td>
<td>A configurable family of RISC-V application/embedded cores targetting FPGA and ASIC technologies</td>
<td>Solderpad</td>
</tr>
<tr>
<td>RVV coprocessor for CVA6</td>
<td><a href="https://github.com/pulp-platform/ara">RVV-coprocessor</a></td>
<td>WI2.4.4</td>
<td>ETH</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>Timing Channel Protection</td>
<td><a href="https://github.com/pulp-platform/cva6">timing-channel-protection</a></td>
<td>WI2.1.1</td>
<td>ETH</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>UVM env for RISC-V verif</td>
<td><a href="https://github.com/openhwgroup/core-v-verif">core-v-verif</a></td>
<td>WI2.4.1</td>
<td>Thales</td>
<td>CVA6 verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>Compression and decompression of digital waveforms</td>
<td><a href="https://github.com/semify-eda/tristan/tree/f6516af367ea9729658724e39aa83fa65c2aa884">Tristan</a></td>
<td>WI2.5.11</td>
<td>semify</td>
<td>Design and Verification in progress</td>
<td></td>
<td>To be determined</td>
</tr>
<tr>
<td>TraceUnit</td>
<td>Not published yet</td>
<td>WI2.1.4, WI2.2.1, WI2.3.4, WI2.5.4</td>
<td>ACCT, FHG, MNRS, SYSGO</td>
<td>Design and Verification in progress</td>
<td></td>
<td>To be determined</td>
</tr>
<tr>
<td>Hypervisor</td>
<td><a href="https://github.com/openhwgroup/cva6">H-extension</a></td>
<td>WI2.5.10</td>
<td>ETH, Sysgo</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>Riviera: RISC-V ISA Extensions for NFC Applications</td>
<td>To Be Done</td>
<td>WI2.5.1</td>
<td>NXP Austria, Politecnico di Torino, Technical University of Graz</td>
<td>Design and Verification in progress</td>
<td></td>
<td>To Be Decided</td>
</tr>
</tbody></table>
<h3 id="peripherals">PERIPHERALS</h3>
<table>
<thead>
<tr>
<th>Repository</th>
<th>URL/Instructions</th>
<th>TRISTAN Working Items</th>
<th>Partners</th>
<th>Status</th>
<th>Description</th>
<th>License</th>
</tr>
</thead>
<tbody><tr>
<td>TSN-TraceBus</td>
<td>Not published yet</td>
<td>WI3.1.1</td>
<td>ACCT, BOSCH-DE, FHG, SYSGO</td>
<td>Design and Verification in progress</td>
<td></td>
<td>To be determined</td>
</tr>
<tr>
<td>HPDcache</td>
<td><a href="https://github.com/openhwgroup/cv-hpdcache">github.com/openhwgroup/cv-hpdcache</a></td>
<td>WI3.1.5</td>
<td>CEA</td>
<td>Design and verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>CLIC</td>
<td><a href="https://github.com/pulp-platform/clic">clic</a></td>
<td>WI3.1.7</td>
<td>ETH</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Apache-2.0</td>
</tr>
<tr>
<td>AXI LLC</td>
<td><a href="https://github.com/pulp-platform/axi_llc">AXI-LLC</a></td>
<td>WI3.1.5</td>
<td>ETH</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>AXI</td>
<td><a href="https://github.com/pulp-platform/axi">AXI</a></td>
<td>WI3.2.1</td>
<td>ETH</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>eFPGA</td>
<td><a href="https://github.com/yongatek/eFPGA">I:Embedded-fpga</a></td>
<td>WI3.4.5</td>
<td>YNGA</td>
<td>Design in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>Accelerator for post-quantum cryptography</td>
<td>To do</td>
<td>WI3.4.4</td>
<td>TUM, Politecnico di Torino</td>
<td>Design in progress</td>
<td></td>
<td>To be determined</td>
</tr>
<tr>
<td>Low-power IO DMA</td>
<td><a href="https://github.com/pulp-platform/udma_core">IO DMA</a></td>
<td>WI3.1.4</td>
<td>UNIBO</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>Heterogeneous Cluster Interconnect (HCI))</td>
<td><a href="https://github.com/pulp-platform/hci">HCI</a></td>
<td>WI3.2.2</td>
<td>UNIBO</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
<tr>
<td>Low-power FP32/FP16 Accelerator for MatMul</td>
<td><a href="https://github.com/pulp-platform/redmule">RedMule</a></td>
<td>WI3.4.1</td>
<td>UNIBO</td>
<td>Design and Verification in progress</td>
<td></td>
<td>Solderpad</td>
</tr>
</tbody></table>
<h3 id="software">SOFTWARE</h3>
<table>
<thead>
<tr>
<th>Repository</th>
<th>URL/Instructions</th>
<th>TRISTAN Working Items</th>
<th>Partners</th>
<th>Status</th>
<th>Description</th>
<th>License</th>
</tr>
</thead>
<tbody><tr>
<td>TimeWeaver</td>
<td><a href="https://www.absint.com/timeweaver/">absint.com/timeweaver</a></td>
<td>WI4.1.5</td>
<td>AbsInt</td>
<td>Waiting for WI4.1.3 / WI2.2.1</td>
<td>TimeWeaver is a hybrid measurement-based timing analysis tool to determine the WCET of safety-critical embedded software. As part of TRISTAN, it will be ported to include support for RISC-V processors using the TRISTAN Trace-IP.</td>
<td>proprietary</td>
</tr>
<tr>
<td>CompCert</td>
<td><a href="https://github.com/AbsInt/CompCert">github.com/AbsInt/CompCert</a></td>
<td>WI4.2.4</td>
<td>AbsInt</td>
<td>Waiting for WI2.5.4</td>
<td>CompCert is a formally-verified optimizing C compiler. As part of TRISTAN, it will be extended to support the HSI (hardware-supported instrumentation) interface of the TRISTAN Trace-IP.</td>
<td>dual licensed (see repository)</td>
</tr>
<tr>
<td>Yocto for CVA6</td>
<td><a href="https://github.com/openhwgroup/meta-cva6-yocto">meta-cva6-yocto</a></td>
<td>WI4.3.3</td>
<td>Thales</td>
<td>Initial release</td>
<td>A linux image for a CVA6-based embedded processor</td>
<td>MIT</td>
</tr>
<tr>
<td>Setting up Yocto and baremetal debug on CVA6</td>
<td><a href="https://github.com/ThalesGroup/cva6-eclipse-demo">cva6-eclipse-demo</a></td>
<td>WI4.3.3</td>
<td>Thales</td>
<td>Initial release</td>
<td>Guidance to set up baremetal and Linux-based debug on CVA6</td>
<td>Apache</td>
</tr>
<tr>
<td>End-to-end stack for ML software development on embedded RISC-V platforms</td>
<td><a href="https://github.com/eml-eda/plinio">Plinio</a></td>
<td>WI4.4.4</td>
<td>Politecnico di Torino, UNIBO</td>
<td>Design in progress</td>
<td></td>
<td>Apache 2.0</td>
</tr>
<tr>
<td>CMSIS like Open-Source AI, as well as DSP- and compute (e.g. BLAS) libraries</td>
<td><a href="https://github.com/eml-eda/RiscV-NN">RiscV-NN</a></td>
<td>WI4.4.1</td>
<td>IFX, Politecnico di Torino, UNIBO, CEA</td>
<td>Design in progress</td>
<td></td>
<td></td>
</tr>
<tr>
<td>COREV GCC</td>
<td><a href="https://github.com/EEESlab/corev-gcc/tree/tristan-dev">COREV GCC (fork)</a></td>
<td>WI4.2.1</td>
<td>UNIBO</td>
<td>Design and Verification in progress</td>
<td></td>
<td>GPL</td>
</tr>
<tr>
<td>COREV Binutils</td>
<td><a href="https://github.com/EEESlab/corev-binutils-gdb/tree/tristan-dev">COREV Binutils (fork)</a></td>
<td>WI4.2.1</td>
<td>UNIBO</td>
<td>Design and Verification in progress</td>
<td></td>
<td>GPL</td>
</tr>
<tr>
<td>ELinOS embedded Linux for RISC-V</td>
<td><a href="https://www.sysgo.com/elinos">ELinOS</a></td>
<td>WI4.3.2</td>
<td>SYSGO</td>
<td>To be released in spring 2024</td>
<td></td>
<td>GPL</td>
</tr>
<tr>
<td>PikeOS CVA-6 support</td>
<td><a href="https://www.pikeos.com/">PikeOS</a></td>
<td>WI4.3.3</td>
<td>SYSGO</td>
<td>To be released</td>
<td></td>
<td>proprietary</td>
</tr>
<tr>
<td>LLVM TD from ADL</td>
<td><a href="https://github.com/nxp-auto-tools/tools_adl">ADLTools</a></td>
<td>WI4.2.1, WI4.2.3</td>
<td>NXP</td>
<td>Design and verification in progress</td>
<td></td>
<td>BSD2</td>
</tr>
<tr>
<td>Cloud Connector</td>
<td><a href="https://github.com/tianhailiu/tristan-automotive-gateway">Cloud Connector</a></td>
<td>WI 4.3.4</td>
<td>aicas</td>
<td>Implementation done. Generating usage documentation in progress</td>
<td></td>
<td>GPL</td>
</tr>
<tr>
<td>RISC-V Runtime</td>
<td>Not published yet</td>
<td>WI4.4.1</td>
<td>CEA</td>
<td>Design and verification in progress</td>
<td></td>
<td>Apache</td>
</tr>
<tr>
<td>VxP Tools and Libraries</td>
<td><a href="https://github.com/CEA-LIST/vxp_binutils.git">VXP binutils</a>, <a href="https://github.com/CEA-LIST/vxp_devkit.git">VXP Devkit</a></td>
<td>WI3.4.2, WI4.2.1, WI4.2.6, WI4.4.1</td>
<td>CEA</td>
<td>Design and verification in progress</td>
<td></td>
<td>Apache</td>
</tr>
</tbody></table>
<h3 id="tools">TOOLS</h3>
<table>
<thead>
<tr>
<th>Tool</th>
<th>URL/Instructions</th>
<th>TRISTAN Working Items</th>
<th>Owner/Contributors</th>
<th>Users</th>
<th>Description</th>
<th>License</th>
<td></td>
</tr>
</thead>
<tbody><tr>
<td>Renode</td>
<td><a href="https://github.com/renode/renode">Renode</a></td>
<td>WI5.1.1</td>
<td>Antmicro</td>
<td>Tampere University, NOKIA, Cargotec</td>
<td>Simulation Framework</td>
<td></td>
</tr>
<tr>
<td>ETISS</td>
<td><a href="https://github.com/tum-ei-eda/etiss">ETISS</a></td>
<td>WI5.1.2</td>
<td>Technische Universität München</td>
<td>Infineon</td>
<td>Extendible Translating Instruction Set Simulator</td>
<td>BSD 3-clause</td>
</tr>
<tr>
<td>SCC</td>
<td><a href="https://github.com/Minres/SystemC-Components">SCC</a></td>
<td>WI5.1.4</td>
<td>Minres</td>
<td>Bosch-DE, CEA</td>
<td>SystemC Components</td>
<td></td>
</tr>
<tr>
<td>PySysC</td>
<td><a href="https://github.com/Minres/PySysC/">PySysC</a></td>
<td>WI5.1.4</td>
<td>Minres</td>
<td>Bosch-DE, CEA</td>
<td>Python bindings for SystemC</td>
<td></td>
</tr>
<tr>
<td>Core DSL</td>
<td><a href="https://github.com/Minres/CoreDSL">Core DSL</a></td>
<td>WI5.1.4</td>
<td>Minres</td>
<td>Bosch-DE, CEA</td>
<td>Language to describe ISAs for ISS generation and HLS of RTL implementation</td>
<td></td>
</tr>
<tr>
<td>DBT-RISE & DBT-RISE-RISCV</td>
<td><a href="https://github.com/Minres/CoreDSL">DBT-RISE</a> <a href="https://github.com/Minres/DBT-RISE-RISCV">DBT-RISE-RISCV</a></td>
<td>WI5.1.4, WI5.3.2</td>
<td>Minres</td>
<td>Bosch-DE, CEA,ACC</td>
<td>Dynamic Binary Translation - Retargetable ISS Environment Application of CoreDSL & DBT-RISE for RISCV</td>
<td></td>
</tr>
<tr>
<td>Verilator</td>
<td><a href="https://www.veripool.org/verilator/">Verilator</a></td>
<td>WI5.2.1</td>
<td>Antmicro</td>
<td>CEA</td>
<td>RTL verification (simulation, formal) Co-simulation with Renode</td>
<td></td>
</tr>
<tr>
<td>Questa Verify Property App</td>
<td><a href="https://eda.sw.siemens.com/en-US/ic/questa/onespin-formal-verification/">Questa</a></td>
<td>WI5.2.2</td>
<td>Siemens EDA</td>
<td>Thales SA</td>
<td>Formal verification solutions for RISC-V (OneSpin)</td>
<td></td>
</tr>
<tr>
<td>Yosys</td>
<td><a href="https://github.com/YosysHQ/yosys">Yosys</a></td>
<td>WI5.2.5</td>
<td>TBD</td>
<td>CEA</td>
<td>Open Synthesis Suite</td>
<td></td>
</tr>
<tr>
<td>Catapult</td>
<td><a href="https://eda.sw.siemens.com/en-US/ic/catapult-high-level-synthesis/">Catapult</a></td>
<td>WI5.2.7</td>
<td>Siemens EDA</td>
<td>Siemens-AT</td>
<td>High Level Synthesis and verification suite</td>
<td></td>
</tr>
<tr>
<td>Kactus2</td>
<td><a href="https://github.com/kactus2/kactus2dev">Kactus2</a></td>
<td>WI5.2.9, WI5.3.3</td>
<td>Minres, Tampere University</td>
<td>Tampere University, NOKIA, Cargotec</td>
<td>High Level Synthesis and verification suite</td>
<td></td>
</tr>
<tr>
<td>Codasip Studio</td>
<td><a href="https://codasip.com/products/codasip-studio/">Codasip Studio</a></td>
<td>WI5.1.3</td>
<td>Codasip</td>
<td>Bosch – DE, Bosch – FR, Minres</td>
<td>Tool suite to develop/customize RISC-V IPs</td>
<td></td>
</tr>
<tr>
<td>GVSOC</td>
<td><a href="https://github.com/EEESlab/gvsoc/tree/tristan-dev">GVSOC (fork)</a></td>
<td>WI5.1.5</td>
<td>UNIBO</td>
<td>Politecnico di Torino</td>
<td>RISC-V Platform Simulator</td>
<td>Apache-2.0</td>
</tr>
<tr>
<td>Messy</td>
<td>TBD</td>
<td>WI5.1.6</td>
<td>Politecnico di Torino</td>
<td>UNIBO</td>
<td>Multi-layer Extra-functional Simulator using SYstemC</td>
<td></td>
</tr>
<tr>
<td>Spike</td>
<td><a href="https://github.com/riscv-software-src/riscv-isa-sim">Spike</a></td>
<td>WI5.1.7</td>
<td>OpenHW Group</td>
<td>Thales, Synthara</td>
<td>RISC-V ISA simulator</td>
<td></td>
</tr>
<tr>
<td>VPTOOL</td>
<td><a href="https://github.com/openhwgroup/core-v-verif">VPTOOL</a></td>
<td>WI5.1.8</td>
<td>OpenHW Group</td>
<td>Thales, Siemens-AT</td>
<td>Graphical edition of a Design Verification Plan </td>
<td></td>
</tr>
<tr>
<td>SoCDSL</td>
<td>TBD</td>
<td>WI5.3.1</td>
<td>Technische Universität Darmstadt</td>
<td>Minres, Tampere University</td>
<td>Automated composition and optimization of compute-intensive SoCs from abstract high-level descriptions </td>
<td></td>
</tr>
<tr>
<td>cv_dv_utils</td>
<td><a href="https://github.com/openhwgroup/core-v-verif">CV_DV_UTILS</a></td>
<td>WI3.1.5</td>
<td>OpenHW Group</td>
<td>CEA</td>
<td>UVM verification environment for OpenHW cores</td>
<td>Apache-2.0</td>
</tr>
<tr>
<td>Co-processor Generator Tool</td>
<td>Not published yet</td>
<td>WI2.5.6</td>
<td>Tampere University</td>
<td>TBD</td>
<td>Tool to generate CV-X-IF compliant co-processors based on user definition of operations/instructions.</td>
<td>TBD</td>
</tr>
</tbody></table>
<h1 id="acknowledgements">Acknowledgements</h1>
<p>TRISTAN has received funding from the Chips Joint Undertaking (Chips JU) under grant agreement nr. 101095947. The Chips JU receives support from the European Union’s Horizon Europe’s research and innovation programmes and participating states are Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Israel, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey.</p>
<p><img src="images/logo_EU.png" alt="EU Logo"> <img src="images/logo_chipsJU.png" alt="ChipsJU_Logo"> </p>
</body>