{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":45276958,"defaultBranch":"master","name":"gcc","ownerLogin":"kraj","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2015-10-30T21:16:25.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/465279?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1716318843.0","currentOid":""},"activityList":{"items":[{"before":"4d207044195b97ecb27c72a7dc987eb8b86644a0","after":"126ccf8ffc46865accec22a2789f09abd98c1d85","ref":"refs/heads/trunk","pushedAt":"2024-06-04T19:15:33.000Z","pushType":"push","commitsCount":16,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"c++: Add testcase for PR103338\n\nThe case in that PR used to ICE until commit f04dc89. This patch simply adds\nthe case to the testsuite.\n\nSuccessfully tested on x86_64-pc-linux-gnu.\n\n\tPR c++/103388\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/parse/crash73.C: New test.","shortMessageHtmlLink":"c++: Add testcase for PR103338"}},{"before":"b2bbf9890ed8a28882ebbf5cc91a507cdb477e5e","after":"c6e6258ea43299399074f8d5f48697b5bc26064e","ref":"refs/heads/releases/gcc-14","pushedAt":"2024-06-04T19:15:02.000Z","pushType":"push","commitsCount":8,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"libstdc++: Only define std::span::at for C++26 [PR115335]\n\nIn r14-5689-g1fa85dcf656e2f I added std::span::at and made the correct\nchanges to the __cpp_lib_span macro (with tests for the correct value in\nC++20/23/26). But I didn't make the declaration of std::span::at\nactually depend on the macro, so it was defined for C++20 and C++23, not\nonly for C++26. This fixes that oversight.\n\nlibstdc++-v3/ChangeLog:\n\n\tPR libstdc++/115335\n\t* include/std/span (span::at): Guard with feature test macro.\n\n(cherry picked from commit 2197814011eec75022aa8550f10621409b69d4a1)","shortMessageHtmlLink":"libstdc++: Only define std::span::at for C++26 [PR115335]"}},{"before":"55b8928721676103ef3ddafda3af0c031d2c9342","after":"c7627054b9ee2ded8a22340a6a09bf9786afcafa","ref":"refs/heads/releases/gcc-12","pushedAt":"2024-06-04T19:14:59.000Z","pushType":"push","commitsCount":6,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"c++: Add testcase for this PR [PR97990]\n\nThis testcase was fixed by r14-5934-gf26d68d5d128c8 but we should add\none to make sure it does not regress again.\n\nCommitted as obvious after a quick test on the testcase.\n\n\tPR c++/97990\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/torture/vector-struct-1.C: New test.\n\nSigned-off-by: Andrew Pinski <quic_apinski@quicinc.com>\n(cherry picked from commit 5f1438db419c9eb8901d1d1d7f98fb69082aec8e)","shortMessageHtmlLink":"c++: Add testcase for this PR [PR97990]"}},{"before":"580865b1c74a96d27f2ad0852ddeb39ec32be8d8","after":"a1fb76e041740e7dd8cdf71dff3ae7aa31b3ea9b","ref":"refs/heads/releases/gcc-11","pushedAt":"2024-06-04T19:14:57.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"rtl-ssa: Fix -fcompare-debug failure [PR100303]\n\nThis patch fixes an oversight in the handling of debug instructions\nin rtl-ssa.  At the moment (and whether this is a good idea or not\nremains to be seen), we maintain a linear RPO sequence of definitions\nand non-debug uses.  If a register is defined more than once, we use\na degenerate phi to reestablish a previous definition where necessary.\n\nHowever, debug instructions shouldn't of course affect codegen,\nso we can't create a new definition just for them.  In those situations\nwe instead hang the debug use off the real definition (meaning that\ndebug uses do not follow a linear order wrt definitions).  Again,\nit remains to be seen whether that's a good idea.\n\nThe problem in the PR was that we weren't taking this into account\nwhen increasing (or potentially increasing) the live range of an\nexisting definition.  We'd create the phi even if it would only\nbe used by debug instructions.\n\nThe patch goes for the simple but inelegant approach of passing\na bool to say whether the use is a debug use or not.  I imagine\nthis area will need some tweaking based on experience in future.\n\ngcc/\n\tPR rtl-optimization/100303\n\t* rtl-ssa/accesses.cc (function_info::make_use_available): Take a\n\tboolean that indicates whether the use will only be used in\n\tdebug instructions.  Treat it in the same way that existing\n\tcross-EBB debug references would be handled if so.\n\t(function_info::make_uses_available): Likewise.\n\t* rtl-ssa/functions.h (function_info::make_uses_available): Update\n\tprototype accordingly.\n\t(function_info::make_uses_available): Likewise.\n\t* fwprop.c (try_fwprop_subst): Update call accordingly.\n\n(cherry picked from commit c97351c0cf4872cc0e99e73ed17fb16659fd38b3)","shortMessageHtmlLink":"rtl-ssa: Fix -fcompare-debug failure [PR100303]"}},{"before":"4d207044195b97ecb27c72a7dc987eb8b86644a0","after":"126ccf8ffc46865accec22a2789f09abd98c1d85","ref":"refs/heads/master","pushedAt":"2024-06-04T19:14:52.000Z","pushType":"push","commitsCount":16,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"c++: Add testcase for PR103338\n\nThe case in that PR used to ICE until commit f04dc89. This patch simply adds\nthe case to the testsuite.\n\nSuccessfully tested on x86_64-pc-linux-gnu.\n\n\tPR c++/103388\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/parse/crash73.C: New test.","shortMessageHtmlLink":"c++: Add testcase for PR103338"}},{"before":"c9ca716498f499ea1178e66694ce90dafeb0a65b","after":"15c8faf3b68bb490711a95ee690edfe1b3b05ebb","ref":"refs/heads/oe/master","pushedAt":"2024-06-04T16:36:17.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>\nSigned-off-by: Khem Raj <raj.khem@gmail.com>","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}},{"before":"6f18642b9032371ea53cf8e406c4e34f46044b4b","after":"628a6aadf5c389581907caa81b1df9dac21e0ea4","ref":"refs/heads/oe/gcc-14","pushedAt":"2024-06-04T16:36:01.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>\nSigned-off-by: Khem Raj <raj.khem@gmail.com>","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}},{"before":"57aa598ceb7bfd74e0bb272b4bc1ee41c3ce986f","after":"2da5c574eeabf25cb669d4677eebc41ff7ffdfbb","ref":"refs/heads/oe/gcc-13","pushedAt":"2024-06-04T16:35:41.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>\nSigned-off-by: Khem Raj <raj.khem@gmail.com>","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}},{"before":"f3d6d60d2ae584a23bb7c681cbd511202953c391","after":"4d207044195b97ecb27c72a7dc987eb8b86644a0","ref":"refs/heads/trunk","pushedAt":"2024-06-04T07:20:17.000Z","pushType":"push","commitsCount":8,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Adjust testcase for -march=cascadelake\n\ngcc/testsuite/ChangeLog:\n\n\tPR target/115299\n\t* gcc.target/i386/pr86722.c: Also scan for blendvpd.","shortMessageHtmlLink":"Adjust testcase for -march=cascadelake"}},{"before":"97474ba2075dc3c397bbc2861646561dcfd13386","after":"b2bbf9890ed8a28882ebbf5cc91a507cdb477e5e","ref":"refs/heads/releases/gcc-14","pushedAt":"2024-06-04T07:19:46.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"ed06ca80bae174f1179222ff8e6b93464006e86a","after":"38360bab8ac3b913d7377902f8d376e2a033c09d","ref":"refs/heads/releases/gcc-13","pushedAt":"2024-06-04T07:19:45.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"c6c2a6cebabc5f78cef3d81cedb4b3b578478b9f","after":"55b8928721676103ef3ddafda3af0c031d2c9342","ref":"refs/heads/releases/gcc-12","pushedAt":"2024-06-04T07:19:43.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"835b913aff1b1a813df3b9d2bbef170ae7d8856d","after":"580865b1c74a96d27f2ad0852ddeb39ec32be8d8","ref":"refs/heads/releases/gcc-11","pushedAt":"2024-06-04T07:19:42.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"f3d6d60d2ae584a23bb7c681cbd511202953c391","after":"4d207044195b97ecb27c72a7dc987eb8b86644a0","ref":"refs/heads/master","pushedAt":"2024-06-04T07:19:36.000Z","pushType":"push","commitsCount":8,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Adjust testcase for -march=cascadelake\n\ngcc/testsuite/ChangeLog:\n\n\tPR target/115299\n\t* gcc.target/i386/pr86722.c: Also scan for blendvpd.","shortMessageHtmlLink":"Adjust testcase for -march=cascadelake"}},{"before":"1f2ca510065a2033bac408eb5a960ef0126f25cc","after":"f3d6d60d2ae584a23bb7c681cbd511202953c391","ref":"refs/heads/trunk","pushedAt":"2024-06-03T19:15:38.000Z","pushType":"push","commitsCount":12,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Implement wrap-around arithmetics in DWARF expressions\n\nFor the following Ada package declaring a simple variable-sized record type:\n\npackage P is\n\n  type Enum is (Zero, One, Two, Three, Four, Five, Six, Seven, Eight, Nine);\n\n  type Rec (Kind : Enum := Zero) is record\n      case Kind is\n        when Four .. Seven =>\n          S : String (1 .. 32);\n        when others =>\n          null;\n      end case;\n    end record;\n\nend P;\n\nthe compiler builds a \"size function\" in GENERIC which is at -Og:\n\nsizetype _GLOBAL.SZ5_p (p__enum p0)\n{\n  return (UNSIGNED_8) p0 + 252 <= 3 ? 32 : 0;\n}\n\nThe UNSIGNED_8-based trick makes it possible to eliminates one branch but\nrelies on the wrap-around arithmetics of UNSIGNED_8.  This size function\nis then translated into a DWARF procedure, but the wrap-around arithmetics\nis dropped on the floor, leading to a wrong size calculation when the DWARF\nprocedure is executed.\n\nThe fix also contains an optimization of unsigned comparisons in DWARF for\nthe case where the type is smaller than the \"generic type\" like here.\n\ngcc/\n\t* dwarf2out.cc (loc_list_from_tree_1) <CEIL_DIV_EXPR>; Add const.\n\t<do_comp_binop>: Use a signed comparison for small unsigned types.\n\tImplement wrap-around arithmetics for small integer types.","shortMessageHtmlLink":"Implement wrap-around arithmetics in DWARF expressions"}},{"before":"218246b50b902a552a30d500e363c6e61176a17c","after":"ed06ca80bae174f1179222ff8e6b93464006e86a","ref":"refs/heads/releases/gcc-13","pushedAt":"2024-06-03T19:14:58.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]\n\nany_divmod instructions are modelled with invalid RTX:\n\n  [(set (match_operand:DI 0 \"register_operand\" \"=c\")\n        (sign_extend:DI (match_operator:SI 3 \"divmod_operator\"\n                        [(match_operand:DI 1 \"register_operand\" \"a\")\n                         (match_operand:DI 2 \"register_operand\" \"b\")])))\n   (clobber (reg:DI 23))\n   (clobber (reg:DI 28))]\n\nwhere SImode divmod_operator (div,mod,udiv,umod) has DImode operands.\n\nWrap input operand with truncate:SI to make machine modes consistent.\n\n\tPR target/115297\n\ngcc/ChangeLog:\n\n\t* config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode\n\toperands 3 and 4 with truncate:SI RTX.\n\t(*divmodsi_internal_er): Ditto for operands 1 and 2.\n\t(*divmodsi_internal_er_1): Ditto.\n\t(*divmodsi_internal): Ditto.\n\t* config/alpha/constraints.md (\"b\"): Correct register\n\tnumber in the description.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/alpha/pr115297.c: New test.\n\n(cherry picked from commit 0ac802064c2a018cf166c37841697e867de65a95)","shortMessageHtmlLink":"alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]"}},{"before":"6cb77b63f83594f13720acf2488951202699268e","after":"c6c2a6cebabc5f78cef3d81cedb4b3b578478b9f","ref":"refs/heads/releases/gcc-12","pushedAt":"2024-06-03T19:14:56.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]\n\nany_divmod instructions are modelled with invalid RTX:\n\n  [(set (match_operand:DI 0 \"register_operand\" \"=c\")\n        (sign_extend:DI (match_operator:SI 3 \"divmod_operator\"\n                        [(match_operand:DI 1 \"register_operand\" \"a\")\n                         (match_operand:DI 2 \"register_operand\" \"b\")])))\n   (clobber (reg:DI 23))\n   (clobber (reg:DI 28))]\n\nwhere SImode divmod_operator (div,mod,udiv,umod) has DImode operands.\n\nWrap input operand with truncate:SI to make machine modes consistent.\n\n\tPR target/115297\n\ngcc/ChangeLog:\n\n\t* config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode\n\toperands 3 and 4 with truncate:SI RTX.\n\t(*divmodsi_internal_er): Ditto for operands 1 and 2.\n\t(*divmodsi_internal_er_1): Ditto.\n\t(*divmodsi_internal): Ditto.\n\t* config/alpha/constraints.md (\"b\"): Correct register\n\tnumber in the description.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/alpha/pr115297.c: New test.\n\n(cherry picked from commit 0ac802064c2a018cf166c37841697e867de65a95)","shortMessageHtmlLink":"alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]"}},{"before":"1792a844da6becdbe919d494c88ea14ab3d9df34","after":"835b913aff1b1a813df3b9d2bbef170ae7d8856d","ref":"refs/heads/releases/gcc-11","pushedAt":"2024-06-03T19:14:54.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]\n\nany_divmod instructions are modelled with invalid RTX:\n\n  [(set (match_operand:DI 0 \"register_operand\" \"=c\")\n        (sign_extend:DI (match_operator:SI 3 \"divmod_operator\"\n                        [(match_operand:DI 1 \"register_operand\" \"a\")\n                         (match_operand:DI 2 \"register_operand\" \"b\")])))\n   (clobber (reg:DI 23))\n   (clobber (reg:DI 28))]\n\nwhere SImode divmod_operator (div,mod,udiv,umod) has DImode operands.\n\nWrap input operand with truncate:SI to make machine modes consistent.\n\n\tPR target/115297\n\ngcc/ChangeLog:\n\n\t* config/alpha/alpha.md (<any_divmod:code>si3): Wrap DImode\n\toperands 3 and 4 with truncate:SI RTX.\n\t(*divmodsi_internal_er): Ditto for operands 1 and 2.\n\t(*divmodsi_internal_er_1): Ditto.\n\t(*divmodsi_internal): Ditto.\n\t* config/alpha/constraints.md (\"b\"): Correct register\n\tnumber in the description.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/alpha/pr115297.c: New test.\n\n(cherry picked from commit 0ac802064c2a018cf166c37841697e867de65a95)","shortMessageHtmlLink":"alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]"}},{"before":"1f2ca510065a2033bac408eb5a960ef0126f25cc","after":"f3d6d60d2ae584a23bb7c681cbd511202953c391","ref":"refs/heads/master","pushedAt":"2024-06-03T19:14:48.000Z","pushType":"push","commitsCount":12,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Implement wrap-around arithmetics in DWARF expressions\n\nFor the following Ada package declaring a simple variable-sized record type:\n\npackage P is\n\n  type Enum is (Zero, One, Two, Three, Four, Five, Six, Seven, Eight, Nine);\n\n  type Rec (Kind : Enum := Zero) is record\n      case Kind is\n        when Four .. Seven =>\n          S : String (1 .. 32);\n        when others =>\n          null;\n      end case;\n    end record;\n\nend P;\n\nthe compiler builds a \"size function\" in GENERIC which is at -Og:\n\nsizetype _GLOBAL.SZ5_p (p__enum p0)\n{\n  return (UNSIGNED_8) p0 + 252 <= 3 ? 32 : 0;\n}\n\nThe UNSIGNED_8-based trick makes it possible to eliminates one branch but\nrelies on the wrap-around arithmetics of UNSIGNED_8.  This size function\nis then translated into a DWARF procedure, but the wrap-around arithmetics\nis dropped on the floor, leading to a wrong size calculation when the DWARF\nprocedure is executed.\n\nThe fix also contains an optimization of unsigned comparisons in DWARF for\nthe case where the type is smaller than the \"generic type\" like here.\n\ngcc/\n\t* dwarf2out.cc (loc_list_from_tree_1) <CEIL_DIV_EXPR>; Add const.\n\t<do_comp_binop>: Use a signed comparison for small unsigned types.\n\tImplement wrap-around arithmetics for small integer types.","shortMessageHtmlLink":"Implement wrap-around arithmetics in DWARF expressions"}},{"before":"47827293551a3ec339617678c8e938c8ca3790f1","after":"1f2ca510065a2033bac408eb5a960ef0126f25cc","ref":"refs/heads/trunk","pushedAt":"2024-06-03T07:14:40.000Z","pushType":"push","commitsCount":11,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Add AVX10.1 target_clones support\n\nSince AVX10 is the first major ISA introduced after AVX-512, we propose\nto add target_clones support for it.\n\nAlthough AVX10.1-256 won't cover 512-bit part of AVX512F, but since\nit is only for priority but not for implication, it won't be an issue.\n\ngcc/ChangeLog:\n\n\t* common/config/i386/i386-common.cc: Change Granite Rapids\n\tseries CPU type to P_PROC_AVX10_1_512.\n\t* common/config/i386/i386-cpuinfo.h (enum feature_priority):\n\tRevise comment part. Add P_AVX10_1_256, P_AVX10_1_512,\n\tP_PROC_AVX10_1_512.\n\t* common/config/i386/i386-isas.h: Link to avx10.1-256, avx10.1-512.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/i386/avx10_1-25.c: New test.\n\t* gcc.target/i386/avx10_1-26.c: Ditto.","shortMessageHtmlLink":"Add AVX10.1 target_clones support"}},{"before":"a31676a5d0df11109557802213999c8311813890","after":"97474ba2075dc3c397bbc2861646561dcfd13386","ref":"refs/heads/releases/gcc-14","pushedAt":"2024-06-03T07:14:08.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Add AVX10.1 target_clones support\n\nSince AVX10 is the first major ISA introduced after AVX-512, we propose\nto add target_clones support for it.\n\nAlthough AVX10.1-256 won't cover 512-bit part of AVX512F, but since\nit is only for priority but not for implication, it won't be an issue.\n\ngcc/ChangeLog:\n\n\t* common/config/i386/i386-common.cc: Change Granite Rapids\n\tseries CPU type to P_PROC_AVX10_1_512.\n\t* common/config/i386/i386-cpuinfo.h (enum feature_priority):\n\tRevise comment part. Add P_AVX10_1_256, P_AVX10_1_512,\n\tP_PROC_AVX10_1_512.\n\t* common/config/i386/i386-isas.h: Link to avx10.1-256, avx10.1-512.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/i386/avx10_1-25.c: New test.\n\t* gcc.target/i386/avx10_1-26.c: Ditto.","shortMessageHtmlLink":"Add AVX10.1 target_clones support"}},{"before":"6634ff0f61bd79df779bc6e6e4c0313ff405b7ba","after":"218246b50b902a552a30d500e363c6e61176a17c","ref":"refs/heads/releases/gcc-13","pushedAt":"2024-06-03T07:14:07.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"6ae274d100638f813fb43d7be2721f7f08135b8c","after":"6cb77b63f83594f13720acf2488951202699268e","ref":"refs/heads/releases/gcc-12","pushedAt":"2024-06-03T07:14:05.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"549f97ed1f35d77d4123bc1e8e7d881c21acc1ac","after":"1792a844da6becdbe919d494c88ea14ab3d9df34","ref":"refs/heads/releases/gcc-11","pushedAt":"2024-06-03T07:14:03.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Daily bump.","shortMessageHtmlLink":"Daily bump."}},{"before":"47827293551a3ec339617678c8e938c8ca3790f1","after":"1f2ca510065a2033bac408eb5a960ef0126f25cc","ref":"refs/heads/master","pushedAt":"2024-06-03T07:13:58.000Z","pushType":"push","commitsCount":11,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Add AVX10.1 target_clones support\n\nSince AVX10 is the first major ISA introduced after AVX-512, we propose\nto add target_clones support for it.\n\nAlthough AVX10.1-256 won't cover 512-bit part of AVX512F, but since\nit is only for priority but not for implication, it won't be an issue.\n\ngcc/ChangeLog:\n\n\t* common/config/i386/i386-common.cc: Change Granite Rapids\n\tseries CPU type to P_PROC_AVX10_1_512.\n\t* common/config/i386/i386-cpuinfo.h (enum feature_priority):\n\tRevise comment part. Add P_AVX10_1_256, P_AVX10_1_512,\n\tP_PROC_AVX10_1_512.\n\t* common/config/i386/i386-isas.h: Link to avx10.1-256, avx10.1-512.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/i386/avx10_1-25.c: New test.\n\t* gcc.target/i386/avx10_1-26.c: Ditto.","shortMessageHtmlLink":"Add AVX10.1 target_clones support"}},{"before":"08d82182204ef442e748abdab45241346f359e3c","after":"c9ca716498f499ea1178e66694ce90dafeb0a65b","ref":"refs/heads/oe/master","pushedAt":"2024-06-03T01:48:15.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>\nSigned-off-by: Khem Raj <raj.khem@gmail.com>","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}},{"before":"41d1dc8a23ce2ed86e41f077bc98ce2b3ceecf38","after":"6f18642b9032371ea53cf8e406c4e34f46044b4b","ref":"refs/heads/oe/gcc-14","pushedAt":"2024-06-03T01:48:02.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>\nSigned-off-by: Khem Raj <raj.khem@gmail.com>","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}},{"before":"4aecec3293119d9eb044418b7465bb5650f46a5b","after":"57aa598ceb7bfd74e0bb272b4bc1ee41c3ce986f","ref":"refs/heads/oe/gcc-13","pushedAt":"2024-06-03T01:47:47.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"gcc testsuite tweaks for mips/OE\n\nDisable loongson-mmi runtine, qemu doesn't appear to fully support them even if some\nof the instruction decoding is there.\n\nAlso disable MSA mips runtime extensions. For some reason qemu appears to accept the test\ncode when it shouldn't. Our selected MIPS cpu for QEMU doesn't support them.\n\nMIPS is unusual in the gcc testsuite as it uses EFFECTIVE_TARGETS and loops\nmultiple times through the vector testsuite. In the case of the two above, we can\ncompile/link them but not run them. Even with the runtime disabled, if the code\nmarks it as a runtime test, it will elevate itself to that. Setting the default\ntarget to compile therefore isn't enough.\n\nTherefore add code to downgrade runtime tests to link tests if the hardware\nsupport isn't there to run them. This avoids thousands of test failures. To do\nthis we have to hook downgrade code into the main test runner.\n\nEnable that downgrading for other cases where hardware to run vector extensions is\nunavailable to remove test failures on other architectures too.\n\nAlso, for gcc.target tests, add checks on wheter loongson or msa code can\nbe run before trying that, allowing downgrading of tests there to work too.\n\nUpstream-Status: Pending\n\n[Parts of the patch may be able to be split off and acceptable to upstream with\ndiscussion. Need to investigate why qemu-user passes the 'bad' instructions']\n\nSigned-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>\nSigned-off-by: Khem Raj <raj.khem@gmail.com>","shortMessageHtmlLink":"gcc testsuite tweaks for mips/OE"}},{"before":"3c7301f947ec27e5427106c8fb053693b1c854af","after":"47827293551a3ec339617678c8e938c8ca3790f1","ref":"refs/heads/trunk","pushedAt":"2024-06-02T19:14:15.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Fix PR c++/109958: ICE taking the address of bound static member function brought into derived class by using-declaration\n\nWe currently ICE upon the following because we don't properly handle the\noverload created for B::f through the using statement.\n\n=== cut here ===\nstruct B { static int f(); };\nstruct D : B { using B::f; };\nvoid f(D d) { &d.f; }\n=== cut here ===\n\nThis patch makes build_class_member_access_expr and cp_build_addr_expr_1 handle\nsuch overloads, and fixes the PR.\n\nSuccessfully tested on x86_64-pc-linux-gnu.\n\n\tPR c++/109958\n\ngcc/cp/ChangeLog:\n\n\t* typeck.cc (build_class_member_access_expr): Handle single OVERLOADs.\n\t(cp_build_addr_expr_1): Likewise.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/overload/using6.C: New test.","shortMessageHtmlLink":"Fix PR c++/109958: ICE taking the address of bound static member func…"}},{"before":"3c7301f947ec27e5427106c8fb053693b1c854af","after":"47827293551a3ec339617678c8e938c8ca3790f1","ref":"refs/heads/master","pushedAt":"2024-06-02T19:13:33.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"kraj","name":"Khem Raj","path":"/kraj","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/465279?s=80&v=4"},"commit":{"message":"Fix PR c++/109958: ICE taking the address of bound static member function brought into derived class by using-declaration\n\nWe currently ICE upon the following because we don't properly handle the\noverload created for B::f through the using statement.\n\n=== cut here ===\nstruct B { static int f(); };\nstruct D : B { using B::f; };\nvoid f(D d) { &d.f; }\n=== cut here ===\n\nThis patch makes build_class_member_access_expr and cp_build_addr_expr_1 handle\nsuch overloads, and fixes the PR.\n\nSuccessfully tested on x86_64-pc-linux-gnu.\n\n\tPR c++/109958\n\ngcc/cp/ChangeLog:\n\n\t* typeck.cc (build_class_member_access_expr): Handle single OVERLOADs.\n\t(cp_build_addr_expr_1): Likewise.\n\ngcc/testsuite/ChangeLog:\n\n\t* g++.dg/overload/using6.C: New test.","shortMessageHtmlLink":"Fix PR c++/109958: ICE taking the address of bound static member func…"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEXGHEGQA","startCursor":null,"endCursor":null}},"title":"Activity · kraj/gcc"}