diff --git a/zstd/_generate/gen.go b/zstd/_generate/gen.go index 2ed517fcdf..4460ec0343 100644 --- a/zstd/_generate/gen.go +++ b/zstd/_generate/gen.go @@ -594,16 +594,25 @@ func (o options) updateLength(name string, brValue, brBitsRead, state reg.GPVirt MOVQ(state, AX.As64()) // So we can grab high bytes. MOVQ(brBitsRead, CX.As64()) MOVQ(brValue, BX) - SHLQ(CX, BX) // BX = br.value << br.bitsRead (part of getBits) - MOVB(AX.As8H(), CX.As8L()) // CX = moB (ofState.addBits(), that is byte #1 of moState) - ADDQ(CX.As64(), brBitsRead) // br.bitsRead += n (part of getBits) - NEGL(CX.As32()) // CX = 64 - n - SHRQ(CX, BX) // BX = (br.value << br.bitsRead) >> (64 - n) -- getBits() result - SHRQ(U8(32), AX) // AX = mo (ofState.baselineInt(), that's the higher dword of moState) + SHLQ(CX, BX) // BX = br.value << br.bitsRead (part of getBits) + MOVB(AX.As8H(), CX.As8L()) // CX = moB (ofState.addBits(), that is byte #1 of moState) + SHRQ(U8(32), AX) // AX = mo (ofState.baselineInt(), that's the higher dword of moState) + // If addBits == 0, skip TESTQ(CX.As64(), CX.As64()) - CMOVQEQ(CX.As64(), BX) // BX is zero if n is zero + JZ(LabelRef(name + "_zero")) + + ADDQ(CX.As64(), brBitsRead) // br.bitsRead += n (part of getBits) + // If overread, skip + CMPQ(brBitsRead, U8(64)) + JA(LabelRef(name + "_zero")) + CMPQ(CX.As64(), U8(64)) + JAE(LabelRef(name + "_zero")) - ADDQ(BX, AX) // AX - mo + br.getBits(moB) + NEGQ(CX.As64()) // CX = 64 - n + SHRQ(CX, BX) // BX = (br.value << br.bitsRead) >> (64 - n) -- getBits() result + ADDQ(BX, AX) // AX - mo + br.getBits(moB) + + Label(name + "_zero") MOVQ(AX, out) // Store result } } diff --git a/zstd/fse_decoder_amd64.go b/zstd/fse_decoder_amd64.go index e74df436cf..c881d28d88 100644 --- a/zstd/fse_decoder_amd64.go +++ b/zstd/fse_decoder_amd64.go @@ -34,8 +34,8 @@ const ( // buildDtable will build the decoding table. func (s *fseDecoder) buildDtable() error { ctx := buildDtableAsmContext{ - stateTable: (*uint16)(&s.stateTable[0]), - norm: (*int16)(&s.norm[0]), + stateTable: &s.stateTable[0], + norm: &s.norm[0], dt: (*uint64)(&s.dt[0]), } code := buildDtable_asm(s, &ctx) diff --git a/zstd/fuzz_test.go b/zstd/fuzz_test.go index 19e77376e2..e44bc3a519 100644 --- a/zstd/fuzz_test.go +++ b/zstd/fuzz_test.go @@ -21,7 +21,6 @@ import ( ) func FuzzDecodeAll(f *testing.F) { - defer cpuinfo.DisableBMI2()() addBytesFromZip(f, "testdata/fuzz/decode-corpus-raw.zip", true) addBytesFromZip(f, "testdata/fuzz/decode-corpus-encoded.zip", false) decLow, err := NewReader(nil, WithDecoderLowmem(true), WithDecoderConcurrency(2), WithDecoderMaxMemory(20<<20), WithDecoderMaxWindow(1<<20), IgnoreChecksum(true)) @@ -57,6 +56,15 @@ func FuzzDecodeAll(f *testing.F) { }) } +func FuzzDecodeAllNoBMI2(f *testing.F) { + if !cpuinfo.HasBMI2() { + f.Skip("No BMI, so already tested") + return + } + defer cpuinfo.DisableBMI2()() + FuzzDecodeAll(f) +} + func FuzzDecoder(f *testing.F) { addBytesFromZip(f, "testdata/fuzz/decode-corpus-raw.zip", true) addBytesFromZip(f, "testdata/fuzz/decode-corpus-encoded.zip", false) diff --git a/zstd/seqdec_amd64.s b/zstd/seqdec_amd64.s index 66dab5e613..dbe86c043f 100644 --- a/zstd/seqdec_amd64.s +++ b/zstd/seqdec_amd64.s @@ -1,7 +1,6 @@ // Code generated by command: go run gen.go -out ../seqdec_amd64.s -pkg=zstd. DO NOT EDIT. //go:build !appengine && !noasm && gc && !noasm -// +build !appengine,!noasm,gc,!noasm // func sequenceDecs_decode_amd64(s *sequenceDecs, br *bitReader, ctx *decodeAsmContext) int // Requires: CMOV @@ -52,34 +51,46 @@ sequenceDecs_decode_amd64_fill_byte_by_byte: sequenceDecs_decode_amd64_fill_end: // Update offset - MOVQ R9, AX - MOVQ BX, CX - MOVQ DX, R15 - SHLQ CL, R15 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R15 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R15 - ADDQ R15, AX - MOVQ AX, 16(R10) + MOVQ R9, AX + MOVQ BX, CX + MOVQ DX, R15 + SHLQ CL, R15 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decode_amd64_of_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decode_amd64_of_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decode_amd64_of_update_zero + NEGQ CX + SHRQ CL, R15 + ADDQ R15, AX + +sequenceDecs_decode_amd64_of_update_zero: + MOVQ AX, 16(R10) // Update match length - MOVQ R8, AX - MOVQ BX, CX - MOVQ DX, R15 - SHLQ CL, R15 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R15 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R15 - ADDQ R15, AX - MOVQ AX, 8(R10) + MOVQ R8, AX + MOVQ BX, CX + MOVQ DX, R15 + SHLQ CL, R15 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decode_amd64_ml_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decode_amd64_ml_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decode_amd64_ml_update_zero + NEGQ CX + SHRQ CL, R15 + ADDQ R15, AX + +sequenceDecs_decode_amd64_ml_update_zero: + MOVQ AX, 8(R10) // Fill bitreader to have enough for the remaining CMPQ SI, $0x08 @@ -107,19 +118,25 @@ sequenceDecs_decode_amd64_fill_2_byte_by_byte: sequenceDecs_decode_amd64_fill_2_end: // Update literal length - MOVQ DI, AX - MOVQ BX, CX - MOVQ DX, R15 - SHLQ CL, R15 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R15 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R15 - ADDQ R15, AX - MOVQ AX, (R10) + MOVQ DI, AX + MOVQ BX, CX + MOVQ DX, R15 + SHLQ CL, R15 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decode_amd64_ll_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decode_amd64_ll_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decode_amd64_ll_update_zero + NEGQ CX + SHRQ CL, R15 + ADDQ R15, AX + +sequenceDecs_decode_amd64_ll_update_zero: + MOVQ AX, (R10) // Fill bitreader for state updates MOVQ R14, (SP) @@ -133,11 +150,11 @@ sequenceDecs_decode_amd64_fill_2_end: // Update Literal Length State MOVBQZX DI, R14 CMPQ R14, $0x09 - JBE assert_check_0_ok_srcline_616 + JBE assert_check_0_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_0_ok_srcline_616: +assert_check_0_ok_srcline_626: SHRQ $0x10, DI MOVWQZX DI, DI LEAQ (BX)(R14*1), CX @@ -150,32 +167,32 @@ assert_check_0_ok_srcline_616: DECL BP ANDQ BP, R15 CMPQ R15, $0x00000200 - JB assert_check_1_ok_srcline_635 + JB assert_check_1_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_1_ok_srcline_635: +assert_check_1_ok_srcline_645: ADDQ R15, DI // Load ctx.llTable MOVQ ctx+16(FP), CX MOVQ (CX), CX CMPQ DI, $0x00000200 - JB assert_check_2_ok_srcline_653 + JB assert_check_2_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_2_ok_srcline_653: +assert_check_2_ok_srcline_663: MOVQ (CX)(DI*8), DI // Update Match Length State MOVBQZX R8, R14 CMPQ R14, $0x09 - JBE assert_check_3_ok_srcline_616 + JBE assert_check_3_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_3_ok_srcline_616: +assert_check_3_ok_srcline_626: SHRQ $0x10, R8 MOVWQZX R8, R8 LEAQ (BX)(R14*1), CX @@ -188,32 +205,32 @@ assert_check_3_ok_srcline_616: DECL BP ANDQ BP, R15 CMPQ R15, $0x00000200 - JB assert_check_4_ok_srcline_635 + JB assert_check_4_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_4_ok_srcline_635: +assert_check_4_ok_srcline_645: ADDQ R15, R8 // Load ctx.mlTable MOVQ ctx+16(FP), CX MOVQ 24(CX), CX CMPQ R8, $0x00000200 - JB assert_check_5_ok_srcline_653 + JB assert_check_5_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_5_ok_srcline_653: +assert_check_5_ok_srcline_663: MOVQ (CX)(R8*8), R8 // Update Offset State MOVBQZX R9, R14 CMPQ R14, $0x09 - JBE assert_check_6_ok_srcline_616 + JBE assert_check_6_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_6_ok_srcline_616: +assert_check_6_ok_srcline_626: SHRQ $0x10, R9 MOVWQZX R9, R9 LEAQ (BX)(R14*1), CX @@ -226,22 +243,22 @@ assert_check_6_ok_srcline_616: DECL BP ANDQ BP, R15 CMPQ R15, $0x00000200 - JB assert_check_7_ok_srcline_635 + JB assert_check_7_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_7_ok_srcline_635: +assert_check_7_ok_srcline_645: ADDQ R15, R9 // Load ctx.ofTable MOVQ ctx+16(FP), CX MOVQ 48(CX), CX CMPQ R9, $0x00000200 - JB assert_check_8_ok_srcline_653 + JB assert_check_8_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_8_ok_srcline_653: +assert_check_8_ok_srcline_663: MOVQ (CX)(R9*8), R9 sequenceDecs_decode_amd64_skip_update: @@ -410,49 +427,67 @@ sequenceDecs_decode_56_amd64_fill_byte_by_byte: sequenceDecs_decode_56_amd64_fill_end: // Update offset - MOVQ R9, AX - MOVQ BX, CX - MOVQ DX, R15 - SHLQ CL, R15 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R15 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R15 - ADDQ R15, AX - MOVQ AX, 16(R10) + MOVQ R9, AX + MOVQ BX, CX + MOVQ DX, R15 + SHLQ CL, R15 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decode_56_amd64_of_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decode_56_amd64_of_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decode_56_amd64_of_update_zero + NEGQ CX + SHRQ CL, R15 + ADDQ R15, AX + +sequenceDecs_decode_56_amd64_of_update_zero: + MOVQ AX, 16(R10) // Update match length - MOVQ R8, AX - MOVQ BX, CX - MOVQ DX, R15 - SHLQ CL, R15 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R15 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R15 - ADDQ R15, AX - MOVQ AX, 8(R10) + MOVQ R8, AX + MOVQ BX, CX + MOVQ DX, R15 + SHLQ CL, R15 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decode_56_amd64_ml_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decode_56_amd64_ml_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decode_56_amd64_ml_update_zero + NEGQ CX + SHRQ CL, R15 + ADDQ R15, AX + +sequenceDecs_decode_56_amd64_ml_update_zero: + MOVQ AX, 8(R10) // Update literal length - MOVQ DI, AX - MOVQ BX, CX - MOVQ DX, R15 - SHLQ CL, R15 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R15 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R15 - ADDQ R15, AX - MOVQ AX, (R10) + MOVQ DI, AX + MOVQ BX, CX + MOVQ DX, R15 + SHLQ CL, R15 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decode_56_amd64_ll_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decode_56_amd64_ll_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decode_56_amd64_ll_update_zero + NEGQ CX + SHRQ CL, R15 + ADDQ R15, AX + +sequenceDecs_decode_56_amd64_ll_update_zero: + MOVQ AX, (R10) // Fill bitreader for state updates MOVQ R14, (SP) @@ -466,11 +501,11 @@ sequenceDecs_decode_56_amd64_fill_end: // Update Literal Length State MOVBQZX DI, R14 CMPQ R14, $0x09 - JBE assert_check_9_ok_srcline_616 + JBE assert_check_9_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_9_ok_srcline_616: +assert_check_9_ok_srcline_626: SHRQ $0x10, DI MOVWQZX DI, DI LEAQ (BX)(R14*1), CX @@ -483,32 +518,32 @@ assert_check_9_ok_srcline_616: DECL BP ANDQ BP, R15 CMPQ R15, $0x00000200 - JB assert_check_10_ok_srcline_635 + JB assert_check_10_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_10_ok_srcline_635: +assert_check_10_ok_srcline_645: ADDQ R15, DI // Load ctx.llTable MOVQ ctx+16(FP), CX MOVQ (CX), CX CMPQ DI, $0x00000200 - JB assert_check_11_ok_srcline_653 + JB assert_check_11_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_11_ok_srcline_653: +assert_check_11_ok_srcline_663: MOVQ (CX)(DI*8), DI // Update Match Length State MOVBQZX R8, R14 CMPQ R14, $0x09 - JBE assert_check_12_ok_srcline_616 + JBE assert_check_12_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_12_ok_srcline_616: +assert_check_12_ok_srcline_626: SHRQ $0x10, R8 MOVWQZX R8, R8 LEAQ (BX)(R14*1), CX @@ -521,32 +556,32 @@ assert_check_12_ok_srcline_616: DECL BP ANDQ BP, R15 CMPQ R15, $0x00000200 - JB assert_check_13_ok_srcline_635 + JB assert_check_13_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_13_ok_srcline_635: +assert_check_13_ok_srcline_645: ADDQ R15, R8 // Load ctx.mlTable MOVQ ctx+16(FP), CX MOVQ 24(CX), CX CMPQ R8, $0x00000200 - JB assert_check_14_ok_srcline_653 + JB assert_check_14_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_14_ok_srcline_653: +assert_check_14_ok_srcline_663: MOVQ (CX)(R8*8), R8 // Update Offset State MOVBQZX R9, R14 CMPQ R14, $0x09 - JBE assert_check_15_ok_srcline_616 + JBE assert_check_15_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_15_ok_srcline_616: +assert_check_15_ok_srcline_626: SHRQ $0x10, R9 MOVWQZX R9, R9 LEAQ (BX)(R14*1), CX @@ -559,22 +594,22 @@ assert_check_15_ok_srcline_616: DECL BP ANDQ BP, R15 CMPQ R15, $0x00000200 - JB assert_check_16_ok_srcline_635 + JB assert_check_16_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_16_ok_srcline_635: +assert_check_16_ok_srcline_645: ADDQ R15, R9 // Load ctx.ofTable MOVQ ctx+16(FP), CX MOVQ 48(CX), CX CMPQ R9, $0x00000200 - JB assert_check_17_ok_srcline_653 + JB assert_check_17_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_17_ok_srcline_653: +assert_check_17_ok_srcline_663: MOVQ (CX)(R9*8), R9 sequenceDecs_decode_56_amd64_skip_update: @@ -833,11 +868,11 @@ sequenceDecs_decode_bmi2_fill_2_end: MOVQ ctx+16(FP), CX MOVQ 48(CX), CX CMPQ R8, $0x00000200 - JB assert_check_18_ok_srcline_686 + JB assert_check_18_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_18_ok_srcline_686: +assert_check_18_ok_srcline_696: MOVQ (CX)(R8*8), R8 // Update Match Length State @@ -851,11 +886,11 @@ assert_check_18_ok_srcline_686: MOVQ ctx+16(FP), CX MOVQ 24(CX), CX CMPQ DI, $0x00000200 - JB assert_check_19_ok_srcline_686 + JB assert_check_19_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_19_ok_srcline_686: +assert_check_19_ok_srcline_696: MOVQ (CX)(DI*8), DI // Update Literal Length State @@ -868,11 +903,11 @@ assert_check_19_ok_srcline_686: MOVQ ctx+16(FP), CX MOVQ (CX), CX CMPQ SI, $0x00000200 - JB assert_check_20_ok_srcline_686 + JB assert_check_20_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_20_ok_srcline_686: +assert_check_20_ok_srcline_696: MOVQ (CX)(SI*8), SI sequenceDecs_decode_bmi2_skip_update: @@ -1106,11 +1141,11 @@ sequenceDecs_decode_56_bmi2_fill_end: MOVQ ctx+16(FP), CX MOVQ 48(CX), CX CMPQ R8, $0x00000200 - JB assert_check_21_ok_srcline_686 + JB assert_check_21_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_21_ok_srcline_686: +assert_check_21_ok_srcline_696: MOVQ (CX)(R8*8), R8 // Update Match Length State @@ -1124,11 +1159,11 @@ assert_check_21_ok_srcline_686: MOVQ ctx+16(FP), CX MOVQ 24(CX), CX CMPQ DI, $0x00000200 - JB assert_check_22_ok_srcline_686 + JB assert_check_22_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_22_ok_srcline_686: +assert_check_22_ok_srcline_696: MOVQ (CX)(DI*8), DI // Update Literal Length State @@ -1141,11 +1176,11 @@ assert_check_22_ok_srcline_686: MOVQ ctx+16(FP), CX MOVQ (CX), CX CMPQ SI, $0x00000200 - JB assert_check_23_ok_srcline_686 + JB assert_check_23_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_23_ok_srcline_686: +assert_check_23_ok_srcline_696: MOVQ (CX)(SI*8), SI sequenceDecs_decode_56_bmi2_skip_update: @@ -1323,21 +1358,21 @@ check_offset: SUBQ DI, R11 JLS copy_match TESTQ R10, R10 - JNZ assert_check_24_ok_srcline_1171 + JNZ assert_check_24_ok_srcline_1181 INT $0x03 INT $0x03 -assert_check_24_ok_srcline_1171: +assert_check_24_ok_srcline_1181: MOVQ R9, R14 SUBQ R11, R14 CMPQ R13, R11 JG copy_all_from_history CMPQ R13, $0x03 - JAE assert_check_25_ok_srcline_1306 + JAE assert_check_25_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_25_ok_srcline_1306: +assert_check_25_ok_srcline_1316: MOVQ R13, R11 SUBQ $0x10, R11 JB copy_4_small @@ -1398,11 +1433,11 @@ copy_4_end: copy_all_from_history: CMPQ R11, $0x01 - JAE assert_check_26_ok_srcline_1306 + JAE assert_check_26_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_26_ok_srcline_1306: +assert_check_26_ok_srcline_1316: MOVQ R11, R15 SUBQ $0x10, R15 JB copy_5_small @@ -1573,11 +1608,11 @@ main_loop: TESTQ R11, R11 JZ check_offset CMPQ R11, $0x01 - JAE assert_check_27_ok_srcline_1306 + JAE assert_check_27_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_27_ok_srcline_1306: +assert_check_27_ok_srcline_1316: MOVQ R11, R14 SUBQ $0x10, R14 JB copy_1_small @@ -1654,21 +1689,21 @@ check_offset: SUBQ DI, R11 JLS copy_match TESTQ R10, R10 - JNZ assert_check_28_ok_srcline_1171 + JNZ assert_check_28_ok_srcline_1181 INT $0x03 INT $0x03 -assert_check_28_ok_srcline_1171: +assert_check_28_ok_srcline_1181: MOVQ R9, R14 SUBQ R11, R14 CMPQ R13, R11 JG copy_all_from_history CMPQ R13, $0x03 - JAE assert_check_29_ok_srcline_1306 + JAE assert_check_29_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_29_ok_srcline_1306: +assert_check_29_ok_srcline_1316: MOVQ R13, R11 SUBQ $0x10, R11 JB copy_4_small @@ -1729,11 +1764,11 @@ copy_4_end: copy_all_from_history: CMPQ R11, $0x01 - JAE assert_check_30_ok_srcline_1306 + JAE assert_check_30_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_30_ok_srcline_1306: +assert_check_30_ok_srcline_1316: MOVQ R11, R15 SUBQ $0x10, R15 JB copy_5_small @@ -1810,11 +1845,11 @@ copy_match: // Copy non-overlapping match ADDQ R13, DI CMPQ R13, $0x01 - JAE assert_check_31_ok_srcline_1306 + JAE assert_check_31_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_31_ok_srcline_1306: +assert_check_31_ok_srcline_1316: MOVQ R13, R12 SUBQ $0x10, R12 JB copy_2_small @@ -1994,34 +2029,46 @@ sequenceDecs_decodeSync_amd64_fill_byte_by_byte: sequenceDecs_decodeSync_amd64_fill_end: // Update offset - MOVQ R9, AX - MOVQ BX, CX - MOVQ DX, R14 - SHLQ CL, R14 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R14 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R14 - ADDQ R14, AX - MOVQ AX, 8(SP) + MOVQ R9, AX + MOVQ BX, CX + MOVQ DX, R14 + SHLQ CL, R14 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decodeSync_amd64_of_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decodeSync_amd64_of_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decodeSync_amd64_of_update_zero + NEGQ CX + SHRQ CL, R14 + ADDQ R14, AX + +sequenceDecs_decodeSync_amd64_of_update_zero: + MOVQ AX, 8(SP) // Update match length - MOVQ R8, AX - MOVQ BX, CX - MOVQ DX, R14 - SHLQ CL, R14 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R14 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R14 - ADDQ R14, AX - MOVQ AX, 16(SP) + MOVQ R8, AX + MOVQ BX, CX + MOVQ DX, R14 + SHLQ CL, R14 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decodeSync_amd64_ml_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decodeSync_amd64_ml_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decodeSync_amd64_ml_update_zero + NEGQ CX + SHRQ CL, R14 + ADDQ R14, AX + +sequenceDecs_decodeSync_amd64_ml_update_zero: + MOVQ AX, 16(SP) // Fill bitreader to have enough for the remaining CMPQ SI, $0x08 @@ -2049,19 +2096,25 @@ sequenceDecs_decodeSync_amd64_fill_2_byte_by_byte: sequenceDecs_decodeSync_amd64_fill_2_end: // Update literal length - MOVQ DI, AX - MOVQ BX, CX - MOVQ DX, R14 - SHLQ CL, R14 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R14 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R14 - ADDQ R14, AX - MOVQ AX, 24(SP) + MOVQ DI, AX + MOVQ BX, CX + MOVQ DX, R14 + SHLQ CL, R14 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decodeSync_amd64_ll_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decodeSync_amd64_ll_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decodeSync_amd64_ll_update_zero + NEGQ CX + SHRQ CL, R14 + ADDQ R14, AX + +sequenceDecs_decodeSync_amd64_ll_update_zero: + MOVQ AX, 24(SP) // Fill bitreader for state updates MOVQ R13, (SP) @@ -2075,11 +2128,11 @@ sequenceDecs_decodeSync_amd64_fill_2_end: // Update Literal Length State MOVBQZX DI, R13 CMPQ R13, $0x09 - JBE assert_check_32_ok_srcline_616 + JBE assert_check_32_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_32_ok_srcline_616: +assert_check_32_ok_srcline_626: SHRQ $0x10, DI MOVWQZX DI, DI LEAQ (BX)(R13*1), CX @@ -2092,32 +2145,32 @@ assert_check_32_ok_srcline_616: DECL R15 ANDQ R15, R14 CMPQ R14, $0x00000200 - JB assert_check_33_ok_srcline_635 + JB assert_check_33_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_33_ok_srcline_635: +assert_check_33_ok_srcline_645: ADDQ R14, DI // Load ctx.llTable MOVQ ctx+16(FP), CX MOVQ (CX), CX CMPQ DI, $0x00000200 - JB assert_check_34_ok_srcline_653 + JB assert_check_34_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_34_ok_srcline_653: +assert_check_34_ok_srcline_663: MOVQ (CX)(DI*8), DI // Update Match Length State MOVBQZX R8, R13 CMPQ R13, $0x09 - JBE assert_check_35_ok_srcline_616 + JBE assert_check_35_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_35_ok_srcline_616: +assert_check_35_ok_srcline_626: SHRQ $0x10, R8 MOVWQZX R8, R8 LEAQ (BX)(R13*1), CX @@ -2130,32 +2183,32 @@ assert_check_35_ok_srcline_616: DECL R15 ANDQ R15, R14 CMPQ R14, $0x00000200 - JB assert_check_36_ok_srcline_635 + JB assert_check_36_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_36_ok_srcline_635: +assert_check_36_ok_srcline_645: ADDQ R14, R8 // Load ctx.mlTable MOVQ ctx+16(FP), CX MOVQ 24(CX), CX CMPQ R8, $0x00000200 - JB assert_check_37_ok_srcline_653 + JB assert_check_37_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_37_ok_srcline_653: +assert_check_37_ok_srcline_663: MOVQ (CX)(R8*8), R8 // Update Offset State MOVBQZX R9, R13 CMPQ R13, $0x09 - JBE assert_check_38_ok_srcline_616 + JBE assert_check_38_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_38_ok_srcline_616: +assert_check_38_ok_srcline_626: SHRQ $0x10, R9 MOVWQZX R9, R9 LEAQ (BX)(R13*1), CX @@ -2168,22 +2221,22 @@ assert_check_38_ok_srcline_616: DECL R15 ANDQ R15, R14 CMPQ R14, $0x00000200 - JB assert_check_39_ok_srcline_635 + JB assert_check_39_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_39_ok_srcline_635: +assert_check_39_ok_srcline_645: ADDQ R14, R9 // Load ctx.ofTable MOVQ ctx+16(FP), CX MOVQ 48(CX), CX CMPQ R9, $0x00000200 - JB assert_check_40_ok_srcline_653 + JB assert_check_40_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_40_ok_srcline_653: +assert_check_40_ok_srcline_663: MOVQ (CX)(R9*8), R9 sequenceDecs_decodeSync_amd64_skip_update: @@ -2211,23 +2264,23 @@ sequenceDecs_decodeSync_amd64_adjust_offset_maybezero: sequenceDecs_decodeSync_amd64_adjust_offset_nonzero: CMPQ R13, $0x00000000 - JAE assert_check_41_ok_srcline_878 + JAE assert_check_41_ok_srcline_888 INT $0x03 INT $0x03 -assert_check_41_ok_srcline_878: +assert_check_41_ok_srcline_888: CMPQ R13, $0x00000000 - JA assert_check_42_ok_srcline_883 + JA assert_check_42_ok_srcline_893 INT $0x03 INT $0x03 -assert_check_42_ok_srcline_883: +assert_check_42_ok_srcline_893: CMPQ R13, $0x00000003 - JBE assert_check_43_ok_srcline_888 + JBE assert_check_43_ok_srcline_898 INT $0x03 INT $0x03 -assert_check_43_ok_srcline_888: +assert_check_43_ok_srcline_898: MOVQ R13, AX XORQ R14, R14 MOVQ $-1, R15 @@ -2235,17 +2288,17 @@ assert_check_43_ok_srcline_888: CMOVQEQ R14, AX CMOVQEQ R15, R14 CMPQ AX, $0x00000000 - JAE assert_check_44_ok_srcline_916 + JAE assert_check_44_ok_srcline_926 INT $0x03 INT $0x03 -assert_check_44_ok_srcline_916: +assert_check_44_ok_srcline_926: CMPQ AX, $0x00000003 - JB assert_check_45_ok_srcline_920 + JB assert_check_45_ok_srcline_930 INT $0x03 INT $0x03 -assert_check_45_ok_srcline_920: +assert_check_45_ok_srcline_930: ADDQ 144(CX)(AX*8), R14 JNZ sequenceDecs_decodeSync_amd64_adjust_temp_valid MOVQ $0x00000001, R14 @@ -2322,21 +2375,21 @@ check_offset: JLS copy_match MOVQ 40(SP), R14 TESTQ R14, R14 - JNZ assert_check_46_ok_srcline_1171 + JNZ assert_check_46_ok_srcline_1181 INT $0x03 INT $0x03 -assert_check_46_ok_srcline_1171: +assert_check_46_ok_srcline_1181: MOVQ 48(SP), R14 SUBQ AX, R14 CMPQ R13, AX JG copy_all_from_history CMPQ R13, $0x03 - JAE assert_check_47_ok_srcline_1306 + JAE assert_check_47_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_47_ok_srcline_1306: +assert_check_47_ok_srcline_1316: MOVQ R13, AX SUBQ $0x10, AX JB copy_4_small @@ -2394,11 +2447,11 @@ copy_4_end: copy_all_from_history: CMPQ AX, $0x01 - JAE assert_check_48_ok_srcline_1306 + JAE assert_check_48_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_48_ok_srcline_1306: +assert_check_48_ok_srcline_1316: MOVQ AX, R15 SUBQ $0x10, R15 JB copy_5_small @@ -2721,11 +2774,11 @@ sequenceDecs_decodeSync_bmi2_fill_2_end: MOVQ ctx+16(FP), CX MOVQ 48(CX), CX CMPQ R8, $0x00000200 - JB assert_check_49_ok_srcline_686 + JB assert_check_49_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_49_ok_srcline_686: +assert_check_49_ok_srcline_696: MOVQ (CX)(R8*8), R8 // Update Match Length State @@ -2739,11 +2792,11 @@ assert_check_49_ok_srcline_686: MOVQ ctx+16(FP), CX MOVQ 24(CX), CX CMPQ DI, $0x00000200 - JB assert_check_50_ok_srcline_686 + JB assert_check_50_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_50_ok_srcline_686: +assert_check_50_ok_srcline_696: MOVQ (CX)(DI*8), DI // Update Literal Length State @@ -2756,11 +2809,11 @@ assert_check_50_ok_srcline_686: MOVQ ctx+16(FP), CX MOVQ (CX), CX CMPQ SI, $0x00000200 - JB assert_check_51_ok_srcline_686 + JB assert_check_51_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_51_ok_srcline_686: +assert_check_51_ok_srcline_696: MOVQ (CX)(SI*8), SI sequenceDecs_decodeSync_bmi2_skip_update: @@ -2788,23 +2841,23 @@ sequenceDecs_decodeSync_bmi2_adjust_offset_maybezero: sequenceDecs_decodeSync_bmi2_adjust_offset_nonzero: CMPQ R13, $0x00000000 - JAE assert_check_52_ok_srcline_878 + JAE assert_check_52_ok_srcline_888 INT $0x03 INT $0x03 -assert_check_52_ok_srcline_878: +assert_check_52_ok_srcline_888: CMPQ R13, $0x00000000 - JA assert_check_53_ok_srcline_883 + JA assert_check_53_ok_srcline_893 INT $0x03 INT $0x03 -assert_check_53_ok_srcline_883: +assert_check_53_ok_srcline_893: CMPQ R13, $0x00000003 - JBE assert_check_54_ok_srcline_888 + JBE assert_check_54_ok_srcline_898 INT $0x03 INT $0x03 -assert_check_54_ok_srcline_888: +assert_check_54_ok_srcline_898: MOVQ R13, R12 XORQ R14, R14 MOVQ $-1, R15 @@ -2812,17 +2865,17 @@ assert_check_54_ok_srcline_888: CMOVQEQ R14, R12 CMOVQEQ R15, R14 CMPQ R12, $0x00000000 - JAE assert_check_55_ok_srcline_916 + JAE assert_check_55_ok_srcline_926 INT $0x03 INT $0x03 -assert_check_55_ok_srcline_916: +assert_check_55_ok_srcline_926: CMPQ R12, $0x00000003 - JB assert_check_56_ok_srcline_920 + JB assert_check_56_ok_srcline_930 INT $0x03 INT $0x03 -assert_check_56_ok_srcline_920: +assert_check_56_ok_srcline_930: ADDQ 144(CX)(R12*8), R14 JNZ sequenceDecs_decodeSync_bmi2_adjust_temp_valid MOVQ $0x00000001, R14 @@ -2899,21 +2952,21 @@ check_offset: JLS copy_match MOVQ 40(SP), R14 TESTQ R14, R14 - JNZ assert_check_57_ok_srcline_1171 + JNZ assert_check_57_ok_srcline_1181 INT $0x03 INT $0x03 -assert_check_57_ok_srcline_1171: +assert_check_57_ok_srcline_1181: MOVQ 48(SP), R14 SUBQ CX, R14 CMPQ R13, CX JG copy_all_from_history CMPQ R13, $0x03 - JAE assert_check_58_ok_srcline_1306 + JAE assert_check_58_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_58_ok_srcline_1306: +assert_check_58_ok_srcline_1316: MOVQ R13, CX SUBQ $0x10, CX JB copy_4_small @@ -2971,11 +3024,11 @@ copy_4_end: copy_all_from_history: CMPQ CX, $0x01 - JAE assert_check_59_ok_srcline_1306 + JAE assert_check_59_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_59_ok_srcline_1306: +assert_check_59_ok_srcline_1316: MOVQ CX, R15 SUBQ $0x10, R15 JB copy_5_small @@ -3208,34 +3261,46 @@ sequenceDecs_decodeSync_safe_amd64_fill_byte_by_byte: sequenceDecs_decodeSync_safe_amd64_fill_end: // Update offset - MOVQ R9, AX - MOVQ BX, CX - MOVQ DX, R14 - SHLQ CL, R14 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R14 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R14 - ADDQ R14, AX - MOVQ AX, 8(SP) + MOVQ R9, AX + MOVQ BX, CX + MOVQ DX, R14 + SHLQ CL, R14 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decodeSync_safe_amd64_of_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decodeSync_safe_amd64_of_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decodeSync_safe_amd64_of_update_zero + NEGQ CX + SHRQ CL, R14 + ADDQ R14, AX + +sequenceDecs_decodeSync_safe_amd64_of_update_zero: + MOVQ AX, 8(SP) // Update match length - MOVQ R8, AX - MOVQ BX, CX - MOVQ DX, R14 - SHLQ CL, R14 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R14 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R14 - ADDQ R14, AX - MOVQ AX, 16(SP) + MOVQ R8, AX + MOVQ BX, CX + MOVQ DX, R14 + SHLQ CL, R14 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decodeSync_safe_amd64_ml_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decodeSync_safe_amd64_ml_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decodeSync_safe_amd64_ml_update_zero + NEGQ CX + SHRQ CL, R14 + ADDQ R14, AX + +sequenceDecs_decodeSync_safe_amd64_ml_update_zero: + MOVQ AX, 16(SP) // Fill bitreader to have enough for the remaining CMPQ SI, $0x08 @@ -3263,19 +3328,25 @@ sequenceDecs_decodeSync_safe_amd64_fill_2_byte_by_byte: sequenceDecs_decodeSync_safe_amd64_fill_2_end: // Update literal length - MOVQ DI, AX - MOVQ BX, CX - MOVQ DX, R14 - SHLQ CL, R14 - MOVB AH, CL - ADDQ CX, BX - NEGL CX - SHRQ CL, R14 - SHRQ $0x20, AX - TESTQ CX, CX - CMOVQEQ CX, R14 - ADDQ R14, AX - MOVQ AX, 24(SP) + MOVQ DI, AX + MOVQ BX, CX + MOVQ DX, R14 + SHLQ CL, R14 + MOVB AH, CL + SHRQ $0x20, AX + TESTQ CX, CX + JZ sequenceDecs_decodeSync_safe_amd64_ll_update_zero + ADDQ CX, BX + CMPQ BX, $0x40 + JA sequenceDecs_decodeSync_safe_amd64_ll_update_zero + CMPQ CX, $0x40 + JAE sequenceDecs_decodeSync_safe_amd64_ll_update_zero + NEGQ CX + SHRQ CL, R14 + ADDQ R14, AX + +sequenceDecs_decodeSync_safe_amd64_ll_update_zero: + MOVQ AX, 24(SP) // Fill bitreader for state updates MOVQ R13, (SP) @@ -3289,11 +3360,11 @@ sequenceDecs_decodeSync_safe_amd64_fill_2_end: // Update Literal Length State MOVBQZX DI, R13 CMPQ R13, $0x09 - JBE assert_check_60_ok_srcline_616 + JBE assert_check_60_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_60_ok_srcline_616: +assert_check_60_ok_srcline_626: SHRQ $0x10, DI MOVWQZX DI, DI LEAQ (BX)(R13*1), CX @@ -3306,32 +3377,32 @@ assert_check_60_ok_srcline_616: DECL R15 ANDQ R15, R14 CMPQ R14, $0x00000200 - JB assert_check_61_ok_srcline_635 + JB assert_check_61_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_61_ok_srcline_635: +assert_check_61_ok_srcline_645: ADDQ R14, DI // Load ctx.llTable MOVQ ctx+16(FP), CX MOVQ (CX), CX CMPQ DI, $0x00000200 - JB assert_check_62_ok_srcline_653 + JB assert_check_62_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_62_ok_srcline_653: +assert_check_62_ok_srcline_663: MOVQ (CX)(DI*8), DI // Update Match Length State MOVBQZX R8, R13 CMPQ R13, $0x09 - JBE assert_check_63_ok_srcline_616 + JBE assert_check_63_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_63_ok_srcline_616: +assert_check_63_ok_srcline_626: SHRQ $0x10, R8 MOVWQZX R8, R8 LEAQ (BX)(R13*1), CX @@ -3344,32 +3415,32 @@ assert_check_63_ok_srcline_616: DECL R15 ANDQ R15, R14 CMPQ R14, $0x00000200 - JB assert_check_64_ok_srcline_635 + JB assert_check_64_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_64_ok_srcline_635: +assert_check_64_ok_srcline_645: ADDQ R14, R8 // Load ctx.mlTable MOVQ ctx+16(FP), CX MOVQ 24(CX), CX CMPQ R8, $0x00000200 - JB assert_check_65_ok_srcline_653 + JB assert_check_65_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_65_ok_srcline_653: +assert_check_65_ok_srcline_663: MOVQ (CX)(R8*8), R8 // Update Offset State MOVBQZX R9, R13 CMPQ R13, $0x09 - JBE assert_check_66_ok_srcline_616 + JBE assert_check_66_ok_srcline_626 INT $0x03 INT $0x03 -assert_check_66_ok_srcline_616: +assert_check_66_ok_srcline_626: SHRQ $0x10, R9 MOVWQZX R9, R9 LEAQ (BX)(R13*1), CX @@ -3382,22 +3453,22 @@ assert_check_66_ok_srcline_616: DECL R15 ANDQ R15, R14 CMPQ R14, $0x00000200 - JB assert_check_67_ok_srcline_635 + JB assert_check_67_ok_srcline_645 INT $0x03 INT $0x03 -assert_check_67_ok_srcline_635: +assert_check_67_ok_srcline_645: ADDQ R14, R9 // Load ctx.ofTable MOVQ ctx+16(FP), CX MOVQ 48(CX), CX CMPQ R9, $0x00000200 - JB assert_check_68_ok_srcline_653 + JB assert_check_68_ok_srcline_663 INT $0x03 INT $0x03 -assert_check_68_ok_srcline_653: +assert_check_68_ok_srcline_663: MOVQ (CX)(R9*8), R9 sequenceDecs_decodeSync_safe_amd64_skip_update: @@ -3425,23 +3496,23 @@ sequenceDecs_decodeSync_safe_amd64_adjust_offset_maybezero: sequenceDecs_decodeSync_safe_amd64_adjust_offset_nonzero: CMPQ R13, $0x00000000 - JAE assert_check_69_ok_srcline_878 + JAE assert_check_69_ok_srcline_888 INT $0x03 INT $0x03 -assert_check_69_ok_srcline_878: +assert_check_69_ok_srcline_888: CMPQ R13, $0x00000000 - JA assert_check_70_ok_srcline_883 + JA assert_check_70_ok_srcline_893 INT $0x03 INT $0x03 -assert_check_70_ok_srcline_883: +assert_check_70_ok_srcline_893: CMPQ R13, $0x00000003 - JBE assert_check_71_ok_srcline_888 + JBE assert_check_71_ok_srcline_898 INT $0x03 INT $0x03 -assert_check_71_ok_srcline_888: +assert_check_71_ok_srcline_898: MOVQ R13, AX XORQ R14, R14 MOVQ $-1, R15 @@ -3449,17 +3520,17 @@ assert_check_71_ok_srcline_888: CMOVQEQ R14, AX CMOVQEQ R15, R14 CMPQ AX, $0x00000000 - JAE assert_check_72_ok_srcline_916 + JAE assert_check_72_ok_srcline_926 INT $0x03 INT $0x03 -assert_check_72_ok_srcline_916: +assert_check_72_ok_srcline_926: CMPQ AX, $0x00000003 - JB assert_check_73_ok_srcline_920 + JB assert_check_73_ok_srcline_930 INT $0x03 INT $0x03 -assert_check_73_ok_srcline_920: +assert_check_73_ok_srcline_930: ADDQ 144(CX)(AX*8), R14 JNZ sequenceDecs_decodeSync_safe_amd64_adjust_temp_valid MOVQ $0x00000001, R14 @@ -3510,11 +3581,11 @@ sequenceDecs_decodeSync_safe_amd64_match_len_ofs_ok: TESTQ AX, AX JZ check_offset CMPQ AX, $0x01 - JAE assert_check_74_ok_srcline_1306 + JAE assert_check_74_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_74_ok_srcline_1306: +assert_check_74_ok_srcline_1316: MOVQ AX, R14 SUBQ $0x10, R14 JB copy_1_small @@ -3593,21 +3664,21 @@ check_offset: JLS copy_match MOVQ 40(SP), R14 TESTQ R14, R14 - JNZ assert_check_75_ok_srcline_1171 + JNZ assert_check_75_ok_srcline_1181 INT $0x03 INT $0x03 -assert_check_75_ok_srcline_1171: +assert_check_75_ok_srcline_1181: MOVQ 48(SP), R14 SUBQ AX, R14 CMPQ R13, AX JG copy_all_from_history CMPQ R13, $0x03 - JAE assert_check_76_ok_srcline_1306 + JAE assert_check_76_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_76_ok_srcline_1306: +assert_check_76_ok_srcline_1316: MOVQ R13, AX SUBQ $0x10, AX JB copy_4_small @@ -3665,11 +3736,11 @@ copy_4_end: copy_all_from_history: CMPQ AX, $0x01 - JAE assert_check_77_ok_srcline_1306 + JAE assert_check_77_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_77_ok_srcline_1306: +assert_check_77_ok_srcline_1316: MOVQ AX, R15 SUBQ $0x10, R15 JB copy_5_small @@ -3746,11 +3817,11 @@ copy_match: // Copy non-overlapping match ADDQ R13, R12 CMPQ R13, $0x01 - JAE assert_check_78_ok_srcline_1306 + JAE assert_check_78_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_78_ok_srcline_1306: +assert_check_78_ok_srcline_1316: MOVQ R13, CX SUBQ $0x10, CX JB copy_2_small @@ -4049,11 +4120,11 @@ sequenceDecs_decodeSync_safe_bmi2_fill_2_end: MOVQ ctx+16(FP), CX MOVQ 48(CX), CX CMPQ R8, $0x00000200 - JB assert_check_79_ok_srcline_686 + JB assert_check_79_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_79_ok_srcline_686: +assert_check_79_ok_srcline_696: MOVQ (CX)(R8*8), R8 // Update Match Length State @@ -4067,11 +4138,11 @@ assert_check_79_ok_srcline_686: MOVQ ctx+16(FP), CX MOVQ 24(CX), CX CMPQ DI, $0x00000200 - JB assert_check_80_ok_srcline_686 + JB assert_check_80_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_80_ok_srcline_686: +assert_check_80_ok_srcline_696: MOVQ (CX)(DI*8), DI // Update Literal Length State @@ -4084,11 +4155,11 @@ assert_check_80_ok_srcline_686: MOVQ ctx+16(FP), CX MOVQ (CX), CX CMPQ SI, $0x00000200 - JB assert_check_81_ok_srcline_686 + JB assert_check_81_ok_srcline_696 INT $0x03 INT $0x03 -assert_check_81_ok_srcline_686: +assert_check_81_ok_srcline_696: MOVQ (CX)(SI*8), SI sequenceDecs_decodeSync_safe_bmi2_skip_update: @@ -4116,23 +4187,23 @@ sequenceDecs_decodeSync_safe_bmi2_adjust_offset_maybezero: sequenceDecs_decodeSync_safe_bmi2_adjust_offset_nonzero: CMPQ R13, $0x00000000 - JAE assert_check_82_ok_srcline_878 + JAE assert_check_82_ok_srcline_888 INT $0x03 INT $0x03 -assert_check_82_ok_srcline_878: +assert_check_82_ok_srcline_888: CMPQ R13, $0x00000000 - JA assert_check_83_ok_srcline_883 + JA assert_check_83_ok_srcline_893 INT $0x03 INT $0x03 -assert_check_83_ok_srcline_883: +assert_check_83_ok_srcline_893: CMPQ R13, $0x00000003 - JBE assert_check_84_ok_srcline_888 + JBE assert_check_84_ok_srcline_898 INT $0x03 INT $0x03 -assert_check_84_ok_srcline_888: +assert_check_84_ok_srcline_898: MOVQ R13, R12 XORQ R14, R14 MOVQ $-1, R15 @@ -4140,17 +4211,17 @@ assert_check_84_ok_srcline_888: CMOVQEQ R14, R12 CMOVQEQ R15, R14 CMPQ R12, $0x00000000 - JAE assert_check_85_ok_srcline_916 + JAE assert_check_85_ok_srcline_926 INT $0x03 INT $0x03 -assert_check_85_ok_srcline_916: +assert_check_85_ok_srcline_926: CMPQ R12, $0x00000003 - JB assert_check_86_ok_srcline_920 + JB assert_check_86_ok_srcline_930 INT $0x03 INT $0x03 -assert_check_86_ok_srcline_920: +assert_check_86_ok_srcline_930: ADDQ 144(CX)(R12*8), R14 JNZ sequenceDecs_decodeSync_safe_bmi2_adjust_temp_valid MOVQ $0x00000001, R14 @@ -4201,11 +4272,11 @@ sequenceDecs_decodeSync_safe_bmi2_match_len_ofs_ok: TESTQ CX, CX JZ check_offset CMPQ CX, $0x01 - JAE assert_check_87_ok_srcline_1306 + JAE assert_check_87_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_87_ok_srcline_1306: +assert_check_87_ok_srcline_1316: MOVQ CX, R14 SUBQ $0x10, R14 JB copy_1_small @@ -4284,21 +4355,21 @@ check_offset: JLS copy_match MOVQ 40(SP), R14 TESTQ R14, R14 - JNZ assert_check_88_ok_srcline_1171 + JNZ assert_check_88_ok_srcline_1181 INT $0x03 INT $0x03 -assert_check_88_ok_srcline_1171: +assert_check_88_ok_srcline_1181: MOVQ 48(SP), R14 SUBQ CX, R14 CMPQ R13, CX JG copy_all_from_history CMPQ R13, $0x03 - JAE assert_check_89_ok_srcline_1306 + JAE assert_check_89_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_89_ok_srcline_1306: +assert_check_89_ok_srcline_1316: MOVQ R13, CX SUBQ $0x10, CX JB copy_4_small @@ -4356,11 +4427,11 @@ copy_4_end: copy_all_from_history: CMPQ CX, $0x01 - JAE assert_check_90_ok_srcline_1306 + JAE assert_check_90_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_90_ok_srcline_1306: +assert_check_90_ok_srcline_1316: MOVQ CX, R15 SUBQ $0x10, R15 JB copy_5_small @@ -4437,11 +4508,11 @@ copy_match: // Copy non-overlapping match ADDQ R13, R11 CMPQ R13, $0x01 - JAE assert_check_91_ok_srcline_1306 + JAE assert_check_91_ok_srcline_1316 INT $0x03 INT $0x03 -assert_check_91_ok_srcline_1306: +assert_check_91_ok_srcline_1316: MOVQ R13, R12 SUBQ $0x10, R12 JB copy_2_small diff --git a/zstd/testdata/fuzz/encode-corpus-encoded.zip b/zstd/testdata/fuzz/encode-corpus-encoded.zip index 5a4316100f..5f2ae9aab6 100644 Binary files a/zstd/testdata/fuzz/encode-corpus-encoded.zip and b/zstd/testdata/fuzz/encode-corpus-encoded.zip differ