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kvm_x86.c
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kvm_x86.c
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/*
* GPL HEADER START
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* GPL HEADER END
*
* Copyright 2011 various Linux Kernel contributors.
* Copyright 2012 Joyent, Inc. All Rights Reserved.
* Copyright 2011 Richard Lowe
*/
#include <sys/types.h>
#include <sys/param.h>
#include <sys/mutex.h>
#include <sys/ksynch.h>
#include <sys/condvar_impl.h>
#include <sys/ddi.h>
#include <sys/regset.h>
#include <sys/fp.h>
#include <sys/tss.h>
#include <vm/page.h>
#include <vm/hat.h>
#include <asm/cpu.h>
#include "kvm_bitops.h"
#include "kvm_vmx.h"
#include "msr-index.h"
#include "kvm_msr.h"
#include "kvm_host.h"
#include "kvm_lapic.h"
#include "processor-flags.h"
#include "kvm_cpuid.h"
#include "hyperv.h"
#include "kvm_apicdef.h"
#include "kvm_iodev.h"
#include "kvm.h"
#include "kvm_x86impl.h"
#include "kvm_irq.h"
#include "kvm_ioapic.h"
#include "kvm_coalesced_mmio.h"
#include "kvm_i8254.h"
#include "kvm_mmu.h"
#include "kvm_cache_regs.h"
extern caddr_t smmap64(caddr_t addr, size_t len, int prot, int flags,
int fd, off_t pos);
extern int memcntl(caddr_t, size_t, int, caddr_t, int, int);
extern int lwp_sigmask(int, uint_t, uint_t, uint_t, uint_t);
extern uint64_t cpu_freq_hz;
static unsigned long empty_zero_page[PAGESIZE / sizeof (unsigned long)];
static uint64_t cpu_tsc_khz;
/*
* Globals
*/
struct kvm_x86_ops *kvm_x86_ops;
int ignore_msrs = 0;
#define MAX_IO_MSRS 256
#define CR0_RESERVED_BITS \
(~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
| X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
| X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
#define CR4_RESERVED_BITS \
(~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
| X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
| X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
| X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
/*
* EFER defaults:
* - enable syscall per default because its emulated by KVM
* - enable LME and LMA per default on 64 bit KVM
*/
static uint64_t efer_reserved_bits = 0xfffffffffffffafeULL;
static void update_cr8_intercept(struct kvm_vcpu *);
static struct kvm_shared_msrs_global shared_msrs_global;
void
kvm_sigprocmask(int how, sigset_t *setp, sigset_t *osetp)
{
k_sigset_t kset;
ASSERT(how == SIG_SETMASK);
ASSERT(setp != NULL);
sigutok(setp, &kset);
if (osetp != NULL)
sigktou(&curthread->t_hold, osetp);
(void) lwp_sigmask(SIG_SETMASK,
kset.__sigbits[0], kset.__sigbits[1], kset.__sigbits[2], 0);
}
static void
kvm_on_user_return(struct kvm_vcpu *vcpu, struct kvm_user_return_notifier *urn)
{
unsigned slot;
struct kvm_shared_msrs *locals =
(struct kvm_shared_msrs *)(((caddr_t)urn) -
offsetof(struct kvm_shared_msrs, urn));
struct kvm_shared_msr_values *values;
for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
values = &locals->values[slot];
if (values->host != values->curr) {
wrmsrl(shared_msrs_global.msrs[slot], values->host);
values->curr = values->host;
}
}
locals->registered = 0;
kvm_user_return_notifier_unregister(vcpu, urn);
}
static void
shared_msr_update(unsigned slot, uint32_t msr)
{
struct kvm_shared_msrs *smsr;
uint64_t value;
smsr = shared_msrs[CPU->cpu_id];
/*
* only read, and nobody should modify it at this time,
* so don't need lock
*/
if (slot >= shared_msrs_global.nr) {
cmn_err(CE_WARN, "kvm: invalid MSR slot!");
return;
}
rdmsrl_safe(msr, (unsigned long long *)&value);
smsr->values[slot].host = value;
smsr->values[slot].curr = value;
}
void
kvm_define_shared_msr(unsigned slot, uint32_t msr)
{
if (slot >= shared_msrs_global.nr)
shared_msrs_global.nr = slot + 1;
shared_msrs_global.msrs[slot] = msr;
/* we need ensured the shared_msr_global have been updated */
smp_wmb();
}
static void
kvm_shared_msr_cpu_online(void)
{
unsigned i;
for (i = 0; i < shared_msrs_global.nr; i++)
shared_msr_update(i, shared_msrs_global.msrs[i]);
}
void
kvm_set_shared_msr(struct kvm_vcpu *vcpu, unsigned slot, uint64_t value,
uint64_t mask)
{
struct kvm_shared_msrs *smsr = shared_msrs[CPU->cpu_id];
if (((value ^ smsr->values[slot].curr) & mask) == 0)
return;
smsr->values[slot].curr = value;
wrmsrl(shared_msrs_global.msrs[slot], value);
if (!smsr->registered) {
smsr->urn.on_user_return = kvm_on_user_return;
kvm_user_return_notifier_register(vcpu, &smsr->urn);
smsr->registered = 1;
}
}
unsigned long
segment_base(uint16_t selector)
{
struct descriptor_table gdt;
struct desc_struct *d;
unsigned long table_base;
unsigned long v;
if (selector == 0)
return (0);
kvm_get_gdt(&gdt);
table_base = gdt.base;
if (selector & 4) { /* from ldt */
uint16_t ldt_selector = kvm_read_ldt();
table_base = segment_base(ldt_selector);
}
d = (struct desc_struct *)(table_base + (selector & ~7));
v = get_desc_base(d);
if (d->c.b.s == 0 &&
(d->c.b.type == 2 || d->c.b.type == 9 || d->c.b.type == 11))
v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
return (v);
}
uint64_t
kvm_get_apic_base(struct kvm_vcpu *vcpu)
{
if (irqchip_in_kernel(vcpu->kvm))
return (vcpu->arch.apic_base);
else
return (vcpu->arch.apic_base);
}
void
kvm_set_apic_base(struct kvm_vcpu *vcpu, uint64_t data)
{
/* TODO: reserve bits check */
if (irqchip_in_kernel(vcpu->kvm))
kvm_lapic_set_base(vcpu, data);
else
vcpu->arch.apic_base = data;
}
#define EXCPT_BENIGN 0
#define EXCPT_CONTRIBUTORY 1
#define EXCPT_PF 2
static int
exception_class(int vector)
{
switch (vector) {
case PF_VECTOR:
return (EXCPT_PF);
case DE_VECTOR:
case TS_VECTOR:
case NP_VECTOR:
case SS_VECTOR:
case GP_VECTOR:
return (EXCPT_CONTRIBUTORY);
default:
break;
}
return (EXCPT_BENIGN);
}
static void
kvm_multiple_exception(struct kvm_vcpu *vcpu,
unsigned nr, int has_error, uint32_t error_code)
{
uint32_t prev_nr;
int class1, class2;
if (!vcpu->arch.exception.pending) {
queue:
vcpu->arch.exception.pending = 1;
vcpu->arch.exception.has_error_code = has_error;
vcpu->arch.exception.nr = nr;
vcpu->arch.exception.error_code = error_code;
return;
}
/* to check exception */
prev_nr = vcpu->arch.exception.nr;
if (prev_nr == DF_VECTOR) {
/* triple fault -> shutdown */
set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
return;
}
class1 = exception_class(prev_nr);
class2 = exception_class(nr);
if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
(class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
/* generate double fault per SDM Table 5-5 */
vcpu->arch.exception.pending = 1;
vcpu->arch.exception.has_error_code = 1;
vcpu->arch.exception.nr = DF_VECTOR;
vcpu->arch.exception.error_code = 0;
} else {
/*
* replace previous exception with a new one in a hope
* that instruction re-execution will regenerate lost
* exception
*/
goto queue;
}
}
void
kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
{
kvm_multiple_exception(vcpu, nr, 0, 0);
}
void
kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
uint32_t error_code)
{
KVM_VCPU_KSTAT_INC(vcpu, kvmvs_pf_guest);
vcpu->arch.cr2 = addr;
kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
}
void
kvm_inject_nmi(struct kvm_vcpu *vcpu)
{
vcpu->arch.nmi_pending = 1;
}
void
kvm_inject_gp(struct kvm_vcpu *vcpu, uint32_t error_code)
{
kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
}
void
kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, uint32_t error_code)
{
kvm_multiple_exception(vcpu, nr, 1, error_code);
}
/*
* Checks if cpl <= required_cpl; if true, return true. Otherwise queue
* a #GP and return false.
*/
int
kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
{
if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
return (1);
kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
return (0);
}
/*
* Load the pae pdptrs. Return true is they are all valid.
*/
int
load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
{
gfn_t pdpt_gfn = cr3 >> PAGESHIFT;
unsigned offset = ((cr3 & (PAGESIZE-1)) >> 5) << 2;
int i;
int ret;
uint64_t pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn,
pdpte, offset * sizeof (uint64_t), sizeof (pdpte));
if (ret < 0) {
ret = 0;
goto out;
}
for (i = 0; i < ARRAY_SIZE(pdpte); i++) {
if (is_present_gpte(pdpte[i]) &&
(pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
ret = 0;
goto out;
}
}
ret = 1;
memcpy(vcpu->arch.pdptrs, pdpte, sizeof (vcpu->arch.pdptrs));
__set_bit(VCPU_EXREG_PDPTR, (unsigned long *)&vcpu->arch.regs_avail);
__set_bit(VCPU_EXREG_PDPTR, (unsigned long *)&vcpu->arch.regs_dirty);
out:
return (ret);
}
static int
pdptrs_changed(struct kvm_vcpu *vcpu)
{
uint64_t pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
if (is_long_mode(vcpu) || !is_pae(vcpu))
return (0);
if (!test_bit(VCPU_EXREG_PDPTR,
(unsigned long *)&vcpu->arch.regs_avail)) {
return (1);
}
if (kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u,
pdpte, sizeof (pdpte)) < 0)
return (1);
return (memcmp(pdpte, vcpu->arch.pdptrs, sizeof (pdpte)) != 0);
}
void
kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
{
cr0 |= X86_CR0_ET;
if (cr0 & 0xffffffff00000000UL) {
kvm_inject_gp(vcpu, 0);
return;
}
cr0 &= ~CR0_RESERVED_BITS;
if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
kvm_inject_gp(vcpu, 0);
return;
}
if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
kvm_inject_gp(vcpu, 0);
return;
}
if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
if ((vcpu->arch.efer & EFER_LME)) {
int cs_db, cs_l;
if (!is_pae(vcpu)) {
kvm_inject_gp(vcpu, 0);
return;
}
kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
if (cs_l) {
kvm_inject_gp(vcpu, 0);
return;
}
} else
if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
kvm_inject_gp(vcpu, 0);
return;
}
}
kvm_x86_ops->set_cr0(vcpu, cr0);
vcpu->arch.cr0 = cr0;
kvm_mmu_reset_context(vcpu);
}
void
kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
{
kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
}
void
kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
{
unsigned long old_cr4 = kvm_read_cr4(vcpu);
unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
if (cr4 & CR4_RESERVED_BITS) {
kvm_inject_gp(vcpu, 0);
return;
}
if (is_long_mode(vcpu)) {
if (!(cr4 & X86_CR4_PAE)) {
kvm_inject_gp(vcpu, 0);
return;
}
} else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) &&
((cr4 ^ old_cr4) & pdptr_bits) &&
!load_pdptrs(vcpu, vcpu->arch.cr3)) {
kvm_inject_gp(vcpu, 0);
return;
}
if (cr4 & X86_CR4_VMXE) {
kvm_inject_gp(vcpu, 0);
return;
}
kvm_x86_ops->set_cr4(vcpu, cr4);
vcpu->arch.cr4 = cr4;
vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
kvm_mmu_reset_context(vcpu);
}
void
kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
{
if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
kvm_mmu_sync_roots(vcpu);
kvm_mmu_flush_tlb(vcpu);
return;
}
if (is_long_mode(vcpu)) {
if (cr3 & CR3_L_MODE_RESERVED_BITS) {
kvm_inject_gp(vcpu, 0);
return;
}
} else {
if (is_pae(vcpu)) {
if (cr3 & CR3_PAE_RESERVED_BITS) {
kvm_inject_gp(vcpu, 0);
return;
}
if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
kvm_inject_gp(vcpu, 0);
return;
}
}
/*
* We don't check reserved bits in nonpae mode, because
* this isn't enforced, and VMware depends on this.
*/
}
/*
* Does the new cr3 value map to physical memory? (Note, we
* catch an invalid cr3 even in real-mode, because it would
* cause trouble later on when we turn on paging anyway.)
*
* A real CPU would silently accept an invalid cr3 and would
* attempt to use it - with largely undefined (and often hard
* to debug) behavior on the guest side.
*/
if ((!gfn_to_memslot(vcpu->kvm, cr3 >> PAGESHIFT)))
kvm_inject_gp(vcpu, 0);
else {
vcpu->arch.cr3 = cr3;
vcpu->arch.mmu.new_cr3(vcpu);
}
}
void
kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
{
if (cr8 & CR8_RESERVED_BITS) {
kvm_inject_gp(vcpu, 0);
return;
}
if (irqchip_in_kernel(vcpu->kvm))
kvm_lapic_set_tpr(vcpu, cr8);
else
vcpu->arch.cr8 = cr8;
}
unsigned long
kvm_get_cr8(struct kvm_vcpu *vcpu)
{
if (irqchip_in_kernel(vcpu->kvm)) {
return (kvm_lapic_get_cr8(vcpu));
} else {
return (vcpu->arch.cr8);
}
}
/*
* List of msr numbers which we expose to userspace through KVM_GET_MSRS
* and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
*
* This list is modified at module load time to reflect the
* capabilities of the host cpu. This capabilities test skips MSRs that are
* kvm-specific. Those are put in the beginning of the list.
*/
#define MSR_KVM_WALL_CLOCK 0x11
#define MSR_KVM_SYSTEM_TIME 0x12
#define KVM_SAVE_MSRS_BEGIN 5
static uint32_t msrs_to_save[] = {
MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
HV_X64_MSR_APIC_ASSIST_PAGE,
MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
MSR_K6_STAR,
MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
};
static unsigned num_msrs_to_save;
static uint32_t emulated_msrs[] = {
MSR_IA32_MISC_ENABLE,
};
static int
set_efer(struct kvm_vcpu *vcpu, uint64_t efer)
{
if (efer & efer_reserved_bits)
return (1);
if (is_paging(vcpu) &&
(vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
return (1);
}
if (efer & EFER_FFXSR) {
struct kvm_cpuid_entry2 *feat;
feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
return (1);
}
if (efer & EFER_SVME) {
struct kvm_cpuid_entry2 *feat;
feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
return (1);
}
efer &= ~EFER_LMA;
efer |= vcpu->arch.efer & EFER_LMA;
kvm_x86_ops->set_efer(vcpu, efer);
vcpu->arch.efer = efer;
vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
kvm_mmu_reset_context(vcpu);
return (0);
}
void
kvm_enable_efer_bits(uint64_t mask)
{
efer_reserved_bits &= ~mask;
}
/*
* Writes msr value into into the appropriate "register".
* Returns 0 on success, non-0 otherwise.
* Assumes vcpu_load() was already called.
*/
int
kvm_set_msr(struct kvm_vcpu *vcpu, uint32_t msr_index, uint64_t data)
{
return (kvm_x86_ops->set_msr(vcpu, msr_index, data));
}
/*
* Adapt set_msr() to msr_io()'s calling convention
*/
static int
do_set_msr(struct kvm_vcpu *vcpu, unsigned index, uint64_t *data)
{
return (kvm_set_msr(vcpu, index, *data));
}
static void
kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
{
int version;
struct pvclock_wall_clock wc;
struct timespec boot;
if (!wall_clock)
return;
if (kvm_read_guest(kvm, wall_clock, &version, sizeof (version)) != 0)
return;
if (version & 1)
version++; /* first time write, random junk */
version++;
kvm_write_guest(kvm, wall_clock, &version, sizeof (version));
/*
* The guest calculates current wall clock time by adding
* system time (updated by kvm_write_guest_time below) to the
* wall clock specified here. guest system time equals host
* system time for us, thus we must fill in host boot time here.
*/
#ifdef XXX
getboottime(&boot);
wc.sec = boot.tv_sec;
wc.nsec = boot.tv_nsec;
wc.version = version;
kvm_write_guest(kvm, wall_clock, &wc, sizeof (wc));
version++;
kvm_write_guest(kvm, wall_clock, &version, sizeof (version));
#else
XXX_KVM_PROBE;
#endif
}
static uint32_t
div_frac(uint32_t dividend, uint32_t divisor)
{
uint32_t quotient, remainder;
/*
* Don't try to replace with do_div(), this one calculates
* "(dividend << 32) / divisor"
*/
__asm__("divl %4"
: "=a" (quotient), "=d" (remainder)
: "0" (0), "1" (dividend), "r" (divisor));
return (quotient);
}
static void
kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
{
uint64_t nsecs = 1000000000LL;
int32_t shift = 0;
uint64_t tps64;
uint32_t tps32;
tps64 = tsc_khz * 1000LL;
while (tps64 > nsecs*2) {
tps64 >>= 1;
shift--;
}
tps32 = (uint32_t)tps64;
while (tps32 <= (uint32_t)nsecs) {
tps32 <<= 1;
shift++;
}
hv_clock->tsc_shift = shift;
hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
}
static void
kvm_write_guest_time(struct kvm_vcpu *v)
{
struct timespec ts;
unsigned long flags;
struct kvm_vcpu_arch *vcpu = &v->arch;
void *shared_kaddr;
unsigned long this_tsc_khz;
if ((!vcpu->time_page))
return;
this_tsc_khz = cpu_tsc_khz;
if (vcpu->hv_clock_tsc_khz != this_tsc_khz) {
kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
vcpu->hv_clock_tsc_khz = this_tsc_khz;
}
#ifdef XXX
/* Keep irq disabled to prevent changes to the clock */
local_irq_save(flags);
#else
/*
* may need to mask interrupts for local_irq_save, and unmask
* for local_irq_restore. cli()/sti() might be done...
*/
XXX_KVM_PROBE;
#endif
kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
gethrestime(&ts);
#ifdef XXX
monotonic_to_bootbased(&ts);
local_irq_restore(flags);
#else
XXX_KVM_PROBE;
#endif
/* With all the info we got, fill in the values */
vcpu->hv_clock.system_time = ts.tv_nsec + (NSEC_PER_SEC *
(uint64_t)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
/*
* The interface expects us to write an even number signaling that the
* update is finished. Since the guest won't see the intermediate
* state, we just increase by 2 at the end.
*/
vcpu->hv_clock.version += 2;
shared_kaddr = page_address(vcpu->time_page);
memcpy((void *)((uintptr_t)shared_kaddr + vcpu->time_offset),
&vcpu->hv_clock, sizeof (vcpu->hv_clock));
mark_page_dirty(v->kvm, vcpu->time >> PAGESHIFT);
}
static int
kvm_request_guest_time_update(struct kvm_vcpu *v)
{
struct kvm_vcpu_arch *vcpu = &v->arch;
if (!vcpu->time_page)
return (0);
set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
return (1);
}
static int
msr_mtrr_valid(unsigned msr)
{
switch (msr) {
case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
case MSR_MTRRfix64K_00000:
case MSR_MTRRfix16K_80000:
case MSR_MTRRfix16K_A0000:
case MSR_MTRRfix4K_C0000:
case MSR_MTRRfix4K_C8000:
case MSR_MTRRfix4K_D0000:
case MSR_MTRRfix4K_D8000:
case MSR_MTRRfix4K_E0000:
case MSR_MTRRfix4K_E8000:
case MSR_MTRRfix4K_F0000:
case MSR_MTRRfix4K_F8000:
case MSR_MTRRdefType:
case MSR_IA32_CR_PAT:
return (1);
case 0x2f8:
return (1);
}
return (0);
}
static int
valid_pat_type(unsigned t)
{
return (t < 8 && (1 << t) & 0xf3); /* 0, 1, 4, 5, 6, 7 */
}
static int
valid_mtrr_type(unsigned t)
{
return (t < 8 && (1 << t) & 0x73); /* 0, 1, 4, 5, 6 */
}
static int
mtrr_valid(struct kvm_vcpu *vcpu, uint32_t msr, uint64_t data)
{
int i;
if (!msr_mtrr_valid(msr))
return (0);
if (msr == MSR_IA32_CR_PAT) {
for (i = 0; i < 8; i++)
if (!valid_pat_type((data >> (i * 8)) & 0xff))
return (0);
return (1);
} else if (msr == MSR_MTRRdefType) {
if (data & ~0xcff)
return (0);
return (valid_mtrr_type(data & 0xff));
} else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
for (i = 0; i < 8; i++)
if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
return (0);
return (1);
}
/* variable MTRRs */
return (valid_mtrr_type(data & 0xff));
}
static int
set_msr_mtrr(struct kvm_vcpu *vcpu, uint32_t msr, uint64_t data)
{
struct mtrr_state_type *state = &vcpu->arch.mtrr_state;
uint64_t *p = (uint64_t *)&state->fixed_ranges;
if (!mtrr_valid(vcpu, msr, data))
return (1);
if (msr == MSR_MTRRdefType) {
state->def_type = data;
state->enabled = (data & 0xc00) >> 10;
} else if (msr == MSR_MTRRfix64K_00000)
p[0] = data;
else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
p[1 + msr - MSR_MTRRfix16K_80000] = data;
else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
p[3 + msr - MSR_MTRRfix4K_C0000] = data;
else if (msr == MSR_IA32_CR_PAT)
vcpu->arch.pat = data;
else { /* Variable MTRRs */
int idx, is_mtrr_mask;
uint64_t *pt;
idx = (msr - 0x200) / 2;
is_mtrr_mask = msr - 0x200 - 2 * idx;
if (!is_mtrr_mask) {
pt = (uint64_t *)&state->var_ranges[idx].base_lo;
} else {
pt = (uint64_t *)&state->var_ranges[idx].mask_lo;
}
*pt = data;
}
kvm_mmu_reset_context(vcpu);
return (0);
}
static int
set_msr_mce(struct kvm_vcpu *vcpu, uint32_t msr, uint64_t data)
{
uint64_t mcg_cap = vcpu->arch.mcg_cap;
unsigned bank_num = mcg_cap & 0xff;
switch (msr) {
case MSR_IA32_MCG_STATUS:
vcpu->arch.mcg_status = data;
break;
case MSR_IA32_MCG_CTL:
if (!(mcg_cap & MCG_CTL_P))
return (1);
/*
* XXX: The SunOS AMD CPU specific module only puts 1 bits in
* the MCG for banks which exist in the system, failing this
* test for no good reason. Userland appears to treat this as
* 0 if it's not all 1's, but that seems no reason to #GP the
* guest...
*
* This is a hack to prevent DEBUG kernels trapping to their
* doom (this, followed by an unaligned trap stack).
*/
#if XXX
if (data != 0 && data != ~(uint64_t)0)
return (-1);
#else
XXX_KVM_PROBE
#endif
vcpu->arch.mcg_ctl = data;
break;
default:
if (msr >= MSR_IA32_MC0_CTL &&
msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
uint32_t offset = msr - MSR_IA32_MC0_CTL;
/*
* only 0 or all 1s can be written to IA32_MCi_CTL
* some Linux kernels though clear bit 10 in bank 4 to
* workaround a BIOS/GART TBL issue on AMD K8s, ignore
* this to avoid an uncatched #GP in the guest
*/
if ((offset & 0x3) == 0 &&
data != 0 && (data | (1 << 10)) != ~(uint64_t)0)
return (-1);
vcpu->arch.mce_banks[offset] = data;
break;
}
return (1);
}
return (0);
}
static int
xen_hvm_config(struct kvm_vcpu *vcpu, uint64_t data)
{
struct kvm *kvm = vcpu->kvm;
int lm = is_long_mode(vcpu);
uint8_t *blob_addr = lm ?
(uint8_t *)(long)kvm->arch.xen_hvm_config.blob_addr_64 :
(uint8_t *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
uint8_t blob_size = lm ?
kvm->arch.xen_hvm_config.blob_size_64 :
kvm->arch.xen_hvm_config.blob_size_32;
uint32_t page_num = data & ~PAGEMASK;
uint64_t page_addr = data & PAGEMASK;
uint8_t *page;
int r;
r = E2BIG;
if (page_num >= blob_size)
goto out;
r = ENOMEM;
page = kmem_alloc(PAGESIZE, KM_SLEEP);