/
lib.rs
4396 lines (3925 loc) · 139 KB
/
lib.rs
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#![no_std]
#![crate_name = "raw_cpuid"]
#![crate_type = "lib"]
#[cfg(test)]
#[macro_use]
extern crate std;
#[cfg(test)]
mod tests;
#[cfg(feature = "serialize")]
#[macro_use]
extern crate serde_derive;
#[macro_use]
extern crate bitflags;
/// Uses Rust's `cpuid` function from the `arch` module.
pub mod native_cpuid {
use super::CpuIdResult;
#[cfg(target_arch = "x86")]
use core::arch::x86 as arch;
#[cfg(target_arch = "x86_64")]
use core::arch::x86_64 as arch;
pub fn cpuid_count(a: u32, c: u32) -> CpuIdResult {
let result = unsafe { self::arch::__cpuid_count(a, c) };
CpuIdResult {
eax: result.eax,
ebx: result.ebx,
ecx: result.ecx,
edx: result.edx,
}
}
}
use core::cmp::min;
use core::fmt;
use core::mem::size_of;
use core::slice;
use core::str;
#[cfg(not(test))]
mod std {
pub use core::ops;
pub use core::option;
}
/// Macro which queries cpuid directly.
///
/// First parameter is cpuid leaf (EAX register value),
/// second optional parameter is the subleaf (ECX register value).
#[macro_export]
macro_rules! cpuid {
($eax:expr) => {
$crate::native_cpuid::cpuid_count($eax as u32, 0)
};
($eax:expr, $ecx:expr) => {
$crate::native_cpuid::cpuid_count($eax as u32, $ecx as u32)
};
}
fn as_bytes(v: &u32) -> &[u8] {
let start = v as *const u32 as *const u8;
unsafe { slice::from_raw_parts(start, 4) }
}
fn get_bits(r: u32, from: u32, to: u32) -> u32 {
assert!(from <= 31);
assert!(to <= 31);
assert!(from <= to);
let mask = match to {
31 => 0xffffffff,
_ => (1 << (to + 1)) - 1,
};
(r & mask) >> from
}
macro_rules! check_flag {
($doc:meta, $fun:ident, $flags:ident, $flag:expr) => {
#[$doc]
pub fn $fun(&self) -> bool {
self.$flags.contains($flag)
}
};
}
macro_rules! is_bit_set {
($field:expr, $bit:expr) => {
$field & (1 << $bit) > 0
};
}
macro_rules! check_bit_fn {
($doc:meta, $fun:ident, $field:ident, $bit:expr) => {
#[$doc]
pub fn $fun(&self) -> bool {
is_bit_set!(self.$field, $bit)
}
};
}
/// Main type used to query for information about the CPU we're running on.
#[derive(Debug, Default)]
#[cfg_attr(feature = "serialize", derive(Serialize, Deserialize))]
pub struct CpuId {
max_eax_value: u32,
}
/// Low-level data-structure to store result of cpuid instruction.
#[derive(Copy, Clone, Debug, Default)]
#[cfg_attr(feature = "serialize", derive(Serialize, Deserialize))]
#[repr(C)]
pub struct CpuIdResult {
/// Return value EAX register
pub eax: u32,
/// Return value EBX register
pub ebx: u32,
/// Return value ECX register
pub ecx: u32,
/// Return value EDX register
pub edx: u32,
}
const EAX_VENDOR_INFO: u32 = 0x0;
const EAX_FEATURE_INFO: u32 = 0x1;
const EAX_CACHE_INFO: u32 = 0x2;
const EAX_PROCESSOR_SERIAL: u32 = 0x3;
const EAX_CACHE_PARAMETERS: u32 = 0x4;
const EAX_MONITOR_MWAIT_INFO: u32 = 0x5;
const EAX_THERMAL_POWER_INFO: u32 = 0x6;
const EAX_STRUCTURED_EXTENDED_FEATURE_INFO: u32 = 0x7;
const EAX_DIRECT_CACHE_ACCESS_INFO: u32 = 0x9;
const EAX_PERFORMANCE_MONITOR_INFO: u32 = 0xA;
const EAX_EXTENDED_TOPOLOGY_INFO: u32 = 0xB;
const EAX_EXTENDED_STATE_INFO: u32 = 0xD;
const EAX_RDT_MONITORING: u32 = 0xF;
const EAX_RDT_ALLOCATION: u32 = 0x10;
const EAX_SGX: u32 = 0x12;
const EAX_TRACE_INFO: u32 = 0x14;
const EAX_TIME_STAMP_COUNTER_INFO: u32 = 0x15;
const EAX_FREQUENCY_INFO: u32 = 0x16;
const EAX_SOC_VENDOR_INFO: u32 = 0x17;
const EAX_DETERMINISTIC_ADDRESS_TRANSLATION_INFO: u32 = 0x18;
const EAX_HYPERVISOR_INFO: u32 = 0x40000000;
const EAX_EXTENDED_FUNCTION_INFO: u32 = 0x80000000;
const EAX_MEMORY_ENCRYPTION_INFO: u32 = 0x8000001F;
impl CpuId {
/// Return new CPUID struct.
pub fn new() -> CpuId {
let res = cpuid!(EAX_VENDOR_INFO);
CpuId {
max_eax_value: res.eax,
}
}
fn leaf_is_supported(&self, val: u32) -> bool {
val <= self.max_eax_value
}
/// Return information about vendor.
/// This is typically a ASCII readable string such as
/// GenuineIntel for Intel CPUs or AuthenticAMD for AMD CPUs.
pub fn get_vendor_info(&self) -> Option<VendorInfo> {
if self.leaf_is_supported(EAX_VENDOR_INFO) {
let res = cpuid!(EAX_VENDOR_INFO);
Some(VendorInfo {
ebx: res.ebx,
ecx: res.ecx,
edx: res.edx,
})
} else {
None
}
}
/// Query a set of features that are available on this CPU.
pub fn get_feature_info(&self) -> Option<FeatureInfo> {
if self.leaf_is_supported(EAX_FEATURE_INFO) {
let res = cpuid!(EAX_FEATURE_INFO);
Some(FeatureInfo {
eax: res.eax,
ebx: res.ebx,
edx_ecx: FeatureInfoFlags {
bits: (((res.edx as u64) << 32) | (res.ecx as u64)),
},
})
} else {
None
}
}
/// Query basic information about caches. This will just return an index
/// into a static table of cache descriptions (see `CACHE_INFO_TABLE`).
pub fn get_cache_info(&self) -> Option<CacheInfoIter> {
if self.leaf_is_supported(EAX_CACHE_INFO) {
let res = cpuid!(EAX_CACHE_INFO);
Some(CacheInfoIter {
current: 1,
eax: res.eax,
ebx: res.ebx,
ecx: res.ecx,
edx: res.edx,
})
} else {
None
}
}
/// Retrieve serial number of processor.
pub fn get_processor_serial(&self) -> Option<ProcessorSerial> {
if self.leaf_is_supported(EAX_PROCESSOR_SERIAL) {
let res = cpuid!(EAX_PROCESSOR_SERIAL);
Some(ProcessorSerial {
ecx: res.ecx,
edx: res.edx,
})
} else {
None
}
}
/// Retrieve more elaborate information about caches (as opposed
/// to `get_cache_info`). This will tell us about associativity,
/// set size, line size etc. for each level of the cache hierarchy.
pub fn get_cache_parameters(&self) -> Option<CacheParametersIter> {
if self.leaf_is_supported(EAX_CACHE_PARAMETERS) {
Some(CacheParametersIter { current: 0 })
} else {
None
}
}
/// Information about how monitor/mwait works on this CPU.
pub fn get_monitor_mwait_info(&self) -> Option<MonitorMwaitInfo> {
if self.leaf_is_supported(EAX_MONITOR_MWAIT_INFO) {
let res = cpuid!(EAX_MONITOR_MWAIT_INFO);
Some(MonitorMwaitInfo {
eax: res.eax,
ebx: res.ebx,
ecx: res.ecx,
edx: res.edx,
})
} else {
None
}
}
/// Query information about thermal and power management features of the CPU.
pub fn get_thermal_power_info(&self) -> Option<ThermalPowerInfo> {
if self.leaf_is_supported(EAX_THERMAL_POWER_INFO) {
let res = cpuid!(EAX_THERMAL_POWER_INFO);
Some(ThermalPowerInfo {
eax: ThermalPowerFeaturesEax { bits: res.eax },
ebx: res.ebx,
ecx: ThermalPowerFeaturesEcx { bits: res.ecx },
edx: res.edx,
})
} else {
None
}
}
/// Find out about more features supported by this CPU.
pub fn get_extended_feature_info(&self) -> Option<ExtendedFeatures> {
if self.leaf_is_supported(EAX_STRUCTURED_EXTENDED_FEATURE_INFO) {
let res = cpuid!(EAX_STRUCTURED_EXTENDED_FEATURE_INFO);
assert!(res.eax == 0);
Some(ExtendedFeatures {
eax: res.eax,
ebx: ExtendedFeaturesEbx { bits: res.ebx },
ecx: ExtendedFeaturesEcx { bits: res.ecx },
edx: res.edx,
})
} else {
None
}
}
/// Direct cache access info.
pub fn get_direct_cache_access_info(&self) -> Option<DirectCacheAccessInfo> {
if self.leaf_is_supported(EAX_DIRECT_CACHE_ACCESS_INFO) {
let res = cpuid!(EAX_DIRECT_CACHE_ACCESS_INFO);
Some(DirectCacheAccessInfo { eax: res.eax })
} else {
None
}
}
/// Info about performance monitoring (how many counters etc.).
pub fn get_performance_monitoring_info(&self) -> Option<PerformanceMonitoringInfo> {
if self.leaf_is_supported(EAX_PERFORMANCE_MONITOR_INFO) {
let res = cpuid!(EAX_PERFORMANCE_MONITOR_INFO);
Some(PerformanceMonitoringInfo {
eax: res.eax,
ebx: PerformanceMonitoringFeaturesEbx { bits: res.ebx },
ecx: res.ecx,
edx: res.edx,
})
} else {
None
}
}
/// Information about topology (how many cores and what kind of cores).
pub fn get_extended_topology_info(&self) -> Option<ExtendedTopologyIter> {
if self.leaf_is_supported(EAX_EXTENDED_TOPOLOGY_INFO) {
Some(ExtendedTopologyIter { level: 0 })
} else {
None
}
}
/// Information for saving/restoring extended register state.
pub fn get_extended_state_info(&self) -> Option<ExtendedStateInfo> {
if self.leaf_is_supported(EAX_EXTENDED_STATE_INFO) {
let res = cpuid!(EAX_EXTENDED_STATE_INFO, 0);
let res1 = cpuid!(EAX_EXTENDED_STATE_INFO, 1);
Some(ExtendedStateInfo {
eax: ExtendedStateInfoXCR0Flags { bits: res.eax },
ebx: res.ebx,
ecx: res.ecx,
edx: res.edx,
eax1: res1.eax,
ebx1: res1.ebx,
ecx1: ExtendedStateInfoXSSFlags { bits: res1.ecx },
edx1: res1.edx,
})
} else {
None
}
}
/// Quality of service informations.
pub fn get_rdt_monitoring_info(&self) -> Option<RdtMonitoringInfo> {
let res = cpuid!(EAX_RDT_MONITORING, 0);
if self.leaf_is_supported(EAX_RDT_MONITORING) {
Some(RdtMonitoringInfo {
ebx: res.ebx,
edx: res.edx,
})
} else {
None
}
}
/// Quality of service enforcement information.
pub fn get_rdt_allocation_info(&self) -> Option<RdtAllocationInfo> {
let res = cpuid!(EAX_RDT_ALLOCATION, 0);
if self.leaf_is_supported(EAX_RDT_ALLOCATION) {
Some(RdtAllocationInfo { ebx: res.ebx })
} else {
None
}
}
pub fn get_sgx_info(&self) -> Option<SgxInfo> {
// Leaf 12H sub-leaf 0 (ECX = 0) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
self.get_extended_feature_info().and_then(|info| {
if self.leaf_is_supported(EAX_SGX) && info.has_sgx() {
let res = cpuid!(EAX_SGX, 0);
let res1 = cpuid!(EAX_SGX, 1);
Some(SgxInfo {
eax: res.eax,
ebx: res.ebx,
ecx: res.ecx,
edx: res.edx,
eax1: res1.eax,
ebx1: res1.ebx,
ecx1: res1.ecx,
edx1: res1.edx,
})
} else {
None
}
})
}
/// Intel Processor Trace Enumeration Information.
pub fn get_processor_trace_info(&self) -> Option<ProcessorTraceInfo> {
let res = cpuid!(EAX_TRACE_INFO, 0);
if self.leaf_is_supported(EAX_TRACE_INFO) {
let res1 = if res.eax >= 1 {
Some(cpuid!(EAX_TRACE_INFO, 1))
} else {
None
};
Some(ProcessorTraceInfo {
eax: res.eax,
ebx: res.ebx,
ecx: res.ecx,
edx: res.edx,
leaf1: res1,
})
} else {
None
}
}
/// Time Stamp Counter/Core Crystal Clock Information.
pub fn get_tsc_info(&self) -> Option<TscInfo> {
let res = cpuid!(EAX_TIME_STAMP_COUNTER_INFO, 0);
if self.leaf_is_supported(EAX_TIME_STAMP_COUNTER_INFO) {
Some(TscInfo {
eax: res.eax,
ebx: res.ebx,
ecx: res.ecx,
})
} else {
None
}
}
/// Processor Frequency Information.
pub fn get_processor_frequency_info(&self) -> Option<ProcessorFrequencyInfo> {
let res = cpuid!(EAX_FREQUENCY_INFO, 0);
if self.leaf_is_supported(EAX_FREQUENCY_INFO) {
Some(ProcessorFrequencyInfo {
eax: res.eax,
ebx: res.ebx,
ecx: res.ecx,
})
} else {
None
}
}
pub fn deterministic_address_translation_info(&self) -> Option<DatIter> {
if self.leaf_is_supported(EAX_DETERMINISTIC_ADDRESS_TRANSLATION_INFO) {
let res = cpuid!(EAX_DETERMINISTIC_ADDRESS_TRANSLATION_INFO, 0);
Some(DatIter {
current: 0,
count: res.eax,
})
} else {
None
}
}
pub fn get_soc_vendor_info(&self) -> Option<SoCVendorInfo> {
let res = cpuid!(EAX_SOC_VENDOR_INFO, 0);
if self.leaf_is_supported(EAX_SOC_VENDOR_INFO) {
Some(SoCVendorInfo {
eax: res.eax,
ebx: res.ebx,
ecx: res.ecx,
edx: res.edx,
})
} else {
None
}
}
pub fn get_hypervisor_info(&self) -> Option<HypervisorInfo> {
let res = cpuid!(EAX_HYPERVISOR_INFO);
if res.eax > 0 {
Some(HypervisorInfo { res: res })
} else {
None
}
}
/// Extended functionality of CPU described here (including more supported features).
/// This also contains a more detailed CPU model identifier.
pub fn get_extended_function_info(&self) -> Option<ExtendedFunctionInfo> {
let res = cpuid!(EAX_EXTENDED_FUNCTION_INFO);
if res.eax == 0 {
return None;
}
let mut ef = ExtendedFunctionInfo {
max_eax_value: res.eax - EAX_EXTENDED_FUNCTION_INFO,
data: [
CpuIdResult {
eax: res.eax,
ebx: res.ebx,
ecx: res.ecx,
edx: res.edx,
},
CpuIdResult {
eax: 0,
ebx: 0,
ecx: 0,
edx: 0,
},
CpuIdResult {
eax: 0,
ebx: 0,
ecx: 0,
edx: 0,
},
CpuIdResult {
eax: 0,
ebx: 0,
ecx: 0,
edx: 0,
},
CpuIdResult {
eax: 0,
ebx: 0,
ecx: 0,
edx: 0,
},
CpuIdResult {
eax: 0,
ebx: 0,
ecx: 0,
edx: 0,
},
CpuIdResult {
eax: 0,
ebx: 0,
ecx: 0,
edx: 0,
},
CpuIdResult {
eax: 0,
ebx: 0,
ecx: 0,
edx: 0,
},
CpuIdResult {
eax: 0,
ebx: 0,
ecx: 0,
edx: 0,
},
],
};
let max_eax_value = min(ef.max_eax_value + 1, ef.data.len() as u32);
for i in 1..max_eax_value {
ef.data[i as usize] = cpuid!(EAX_EXTENDED_FUNCTION_INFO + i);
}
Some(ef)
}
pub fn get_memory_encryption_info(&self) -> Option<MemoryEncryptionInfo> {
let res = cpuid!(EAX_EXTENDED_FUNCTION_INFO);
if res.eax < EAX_MEMORY_ENCRYPTION_INFO {
return None;
}
let res = cpuid!(EAX_MEMORY_ENCRYPTION_INFO);
Some(MemoryEncryptionInfo {
eax: MemoryEncryptionInfoEax { bits: res.eax },
ebx: res.ebx,
ecx: res.ecx,
edx: res.edx,
})
}
}
#[derive(Debug, Default)]
#[cfg_attr(feature = "serialize", derive(Serialize, Deserialize))]
#[repr(C)]
pub struct VendorInfo {
ebx: u32,
edx: u32,
ecx: u32,
}
impl VendorInfo {
/// Return vendor identification as human readable string.
pub fn as_string<'a>(&'a self) -> &'a str {
let brand_string_start = self as *const VendorInfo as *const u8;
unsafe {
// Safety: VendorInfo is laid out with repr(C).
let slice: &'a [u8] = slice::from_raw_parts(brand_string_start, size_of::<VendorInfo>());
// Safety: The field is specified to be ASCII, and the only safe
// way to construct VendorInfo is from real CPUID data or the
// Default implementation.
str::from_utf8_unchecked(slice)
}
}
}
/// Used to iterate over cache information contained in cpuid instruction.
#[derive(Debug, Default)]
#[cfg_attr(feature = "serialize", derive(Serialize, Deserialize))]
pub struct CacheInfoIter {
current: u32,
eax: u32,
ebx: u32,
ecx: u32,
edx: u32,
}
impl Iterator for CacheInfoIter {
type Item = CacheInfo;
/// Iterate over all cache information.
fn next(&mut self) -> Option<CacheInfo> {
// Every byte of the 4 register values returned by cpuid
// can contain information about a cache (except the
// very first one).
if self.current >= 4 * 4 {
return None;
}
let reg_index = self.current % 4;
let byte_index = self.current / 4;
let reg = match reg_index {
0 => self.eax,
1 => self.ebx,
2 => self.ecx,
3 => self.edx,
_ => unreachable!(),
};
let byte = as_bytes(®)[byte_index as usize];
if byte == 0 {
self.current += 1;
return self.next();
}
for cache_info in CACHE_INFO_TABLE.iter() {
if cache_info.num == byte {
self.current += 1;
return Some(*cache_info);
}
}
None
}
}
/// What type of cache are we dealing with?
#[derive(Copy, Clone, Debug)]
#[cfg_attr(feature = "serialize", derive(Serialize, Deserialize))]
pub enum CacheInfoType {
General,
Cache,
TLB,
STLB,
DTLB,
Prefetch,
}
impl Default for CacheInfoType {
fn default() -> CacheInfoType {
CacheInfoType::General
}
}
/// Describes any kind of cache (TLB, Data and Instruction caches plus prefetchers).
#[derive(Copy, Clone, Debug, Default)]
#[cfg_attr(feature = "serialize", derive(Serialize, Deserialize))]
pub struct CacheInfo {
/// Number as retrieved from cpuid
pub num: u8,
/// Cache type
pub typ: CacheInfoType,
}
impl CacheInfo {
/// Description of the cache (from Intel Manual)
pub fn desc(&self) -> &'static str {
match self.num {
0x00 => "Null descriptor, this byte contains no information",
0x01 => "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries",
0x02 => "Instruction TLB: 4 MByte pages, fully associative, 2 entries",
0x03 => "Data TLB: 4 KByte pages, 4-way set associative, 64 entries",
0x04 => "Data TLB: 4 MByte pages, 4-way set associative, 8 entries",
0x05 => "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries",
0x06 => "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size",
0x08 => "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size",
0x09 => "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size",
0x0A => "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size",
0x0B => "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries",
0x0C => "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size",
0x0D => "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size",
0x0E => "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size",
0x1D => "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size",
0x21 => "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size",
0x22 => "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector",
0x23 => "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector",
0x24 => "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size",
0x25 => "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector",
0x29 => "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector",
0x2C => "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size",
0x30 => "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size",
0x40 => "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache",
0x41 => "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size",
0x42 => "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size",
0x43 => "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size",
0x44 => "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size",
0x45 => "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size",
0x46 => "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size",
0x47 => "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size",
0x48 => "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size",
0x49 => "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H); 2nd-level cache: 4 MByte, 16-way set ssociative, 64 byte line size",
0x4A => "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size",
0x4B => "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size",
0x4C => "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size",
0x4D => "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size",
0x4E => "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size",
0x4F => "Instruction TLB: 4 KByte pages, 32 entries",
0x50 => "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries",
0x51 => "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries",
0x52 => "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries",
0x55 => "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries",
0x56 => "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries",
0x57 => "Data TLB0: 4 KByte pages, 4-way associative, 16 entries",
0x59 => "Data TLB0: 4 KByte pages, fully associative, 16 entries",
0x5A => "Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries",
0x5B => "Data TLB: 4 KByte and 4 MByte pages, 64 entries",
0x5C => "Data TLB: 4 KByte and 4 MByte pages,128 entries",
0x5D => "Data TLB: 4 KByte and 4 MByte pages,256 entries",
0x60 => "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size",
0x61 => "Instruction TLB: 4 KByte pages, fully associative, 48 entries",
0x63 => "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries",
0x64 => "Data TLB: 4 KByte pages, 4-way set associative, 512 entries",
0x66 => "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size",
0x67 => "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size",
0x68 => "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size",
0x6A => "uTLB: 4 KByte pages, 8-way set associative, 64 entries",
0x6B => "DTLB: 4 KByte pages, 8-way set associative, 256 entries",
0x6C => "DTLB: 2M/4M pages, 8-way set associative, 128 entries",
0x6D => "DTLB: 1 GByte pages, fully associative, 16 entries",
0x70 => "Trace cache: 12 K-μop, 8-way set associative",
0x71 => "Trace cache: 16 K-μop, 8-way set associative",
0x72 => "Trace cache: 32 K-μop, 8-way set associative",
0x76 => "Instruction TLB: 2M/4M pages, fully associative, 8 entries",
0x78 => "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size",
0x79 => "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector",
0x7A => "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector",
0x7B => "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector",
0x7C => "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector",
0x7D => "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size",
0x7F => "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size",
0x80 => "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size",
0x82 => "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size",
0x83 => "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size",
0x84 => "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size",
0x85 => "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size",
0x86 => "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size",
0x87 => "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size",
0xA0 => "DTLB: 4k pages, fully associative, 32 entries",
0xB0 => "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries",
0xB1 => "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries",
0xB2 => "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries",
0xB3 => "Data TLB: 4 KByte pages, 4-way set associative, 128 entries",
0xB4 => "Data TLB1: 4 KByte pages, 4-way associative, 256 entries",
0xB5 => "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries",
0xB6 => "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries",
0xBA => "Data TLB1: 4 KByte pages, 4-way associative, 64 entries",
0xC0 => "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries",
0xC1 => "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries",
0xC2 => "DTLB: 2 MByte/$MByte pages, 4-way associative, 16 entries",
0xC3 => "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.",
0xC4 => "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries",
0xCA => "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries",
0xD0 => "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size",
0xD1 => "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size",
0xD2 => "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size",
0xD6 => "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size",
0xD7 => "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size",
0xD8 => "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size",
0xDC => "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size",
0xDD => "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size",
0xDE => "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size",
0xE2 => "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size",
0xE3 => "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size",
0xE4 => "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size",
0xEA => "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size",
0xEB => "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size",
0xEC => "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size",
0xF0 => "64-Byte prefetching",
0xF1 => "128-Byte prefetching",
0xFE => "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters.",
0xFF => "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters",
_ => "Unknown cache type!"
}
}
}
impl fmt::Display for CacheInfo {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
let typ = match self.typ {
CacheInfoType::General => "N/A",
CacheInfoType::Cache => "Cache",
CacheInfoType::TLB => "TLB",
CacheInfoType::STLB => "STLB",
CacheInfoType::DTLB => "DTLB",
CacheInfoType::Prefetch => "Prefetcher",
};
write!(f, "{:x}:\t {}: {}", self.num, typ, self.desc())
}
}
/// This table is taken from Intel manual (Section CPUID instruction).
pub const CACHE_INFO_TABLE: [CacheInfo; 108] = [
CacheInfo {
num: 0x00,
typ: CacheInfoType::General,
},
CacheInfo {
num: 0x01,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x02,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x03,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x04,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x05,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x06,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x08,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x09,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x0A,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x0B,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x0C,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x0D,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x0E,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x21,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x22,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x23,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x24,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x25,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x29,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x2C,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x30,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x40,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x41,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x42,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x43,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x44,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x45,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x46,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x47,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x48,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x49,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x4A,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x4B,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x4C,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x4D,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x4E,
typ: CacheInfoType::Cache,
},
CacheInfo {
num: 0x4F,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x50,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x51,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x52,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x55,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x56,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x57,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x59,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x5A,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x5B,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x5C,
typ: CacheInfoType::TLB,
},
CacheInfo {
num: 0x5D,
typ: CacheInfoType::TLB,