HIL testing issues on different targets

[SergioGasquez]

Failing Tests

• ESP32-S2: spi_full_duplex_dma
  • test_symmetric_dma_transfer_huge_buffer
    If we add the following code:

    --- a/hil-test/tests/spi_full_duplex_dma.rs
    +++ b/hil-test/tests/spi_full_duplex_dma.rs
    @@ -121,6 +121,8 @@ mod tests {
             let transfer = spi.dma_transfer(&mut send, &mut receive).unwrap();
             transfer.wait().unwrap();
             assert_eq!(send[0..1], receive[0..1]);
    +        let transfer = spi.dma_transfer(&mut send, &mut receive).unwrap();
    +        transfer.wait().unwrap();
         }

    The issue disappears, but not sure if that's the root cause of the issue because this is not required in other targets.
  • test_symmetric_dma_transfer fails if previous test failed
    Im not sure what triggers this, but I think that when some test failed, the init state is bad and the first test of spi_full_duplex_dma fails.

    running 3 tests
    test tests::test_symmetric_dma_transfer             ... ERROR panicked at 'assertion failed: `(left == right)`'
    diff < left / right >
    <[222, 173, 190, 239]
    >[0, 0, 0, 0]
    └─ spi_full_duplex_dma::tests::test_symmetric_dma_transfer @ tests/spi_full_duplex_dma.rs:81  
    

• ESP32-S2: delay
  Intermittently fails the delay_700millis test. See https://github.com/esp-rs/esp-hal/actions/runs/8880612772/job/24381385302
• ESP32-C3/ESP32-C2: uart::test_send_receive_different_baud_rates_and_clock_sources
  When using the RcFast clock source, the code just hangs in https://github.com/esp-rs/esp-hal/blob/main/esp-hal/src/uart.rs#L1108 and then, the test times out. The reg_update should: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. but looks like its never cleared because it's not synchronized.
• ESP32-S3/ESP32-S2: gpio::test_gpio_interrupt (GPIO test test_gpio_interrupt is failing for Xtensa targets #1413)
• ESP32-H2: get_time (ESP32-H2: Delay::delay_millis delays too short #1509)
• ESP32/ESP32-S2 i2s issue
• ESP32-H2 i2s: ESP32-H2: I2S Clock is way too slow #1637

[MabezDev]

There are FIFO access issues on the S2 with uart, maybe there is something similar here?

[SergioGasquez]

There are FIFO access issues on the S2 with uart, maybe there is something similar here?

They could definitely be related, is there a tracking issue for that?