/
common.rs
162 lines (134 loc) · 4.17 KB
/
common.rs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
use crate::arch::ppc::reg::PpcVector;
use crate::arch::RawRegId;
use crate::arch::Registers;
use core::convert::TryInto;
/// 32-bit PowerPC core registers, FPU registers, and AltiVec SIMD registers.
///
/// Sources:
/// * https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/powerpc-altivec32.xml
/// * https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/power-core.xml
/// * https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/power-fpu.xml
/// * https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/power-altivec.xml
#[derive(Debug, Default, Clone, PartialEq)]
pub struct PowerPcCommonRegs {
/// General purpose registers
pub r: [u32; 32],
/// Floating Point registers
pub f: [f64; 32],
/// Program counter
pub pc: u32,
/// Machine state
pub msr: u32,
/// Condition register
pub cr: u32,
/// Link register
pub lr: u32,
/// Count register
pub ctr: u32,
/// Integer exception register
pub xer: u32,
/// Floating-point status and control register
pub fpscr: u32,
/// Vector registers
pub vr: [PpcVector; 32],
/// Vector status and control register
pub vscr: u32,
/// Vector context save register
pub vrsave: u32,
}
impl Registers for PowerPcCommonRegs {
type RegId = RawRegId;
fn gdb_serialize(&self, mut write_byte: impl FnMut(Option<u8>)) {
macro_rules! write_bytes {
($bytes:expr) => {
for b in $bytes {
write_byte(Some(*b))
}
};
}
macro_rules! write_regs {
($($reg:ident),*) => {
$(
write_bytes!(&self.$reg.to_be_bytes());
)*
}
}
for reg in &self.r {
write_bytes!(®.to_be_bytes());
}
for reg in &self.f {
write_bytes!(®.to_be_bytes());
}
write_regs!(pc, msr, cr, lr, ctr, xer, fpscr);
for ® in &self.vr {
let reg: u128 = reg;
write_bytes!(®.to_be_bytes());
}
write_regs!(vscr, vrsave);
}
fn gdb_deserialize(&mut self, bytes: &[u8]) -> Result<(), ()> {
if bytes.len() < 0x3a4 {
return Err(());
}
let mut regs = bytes[0..0x80]
.chunks_exact(4)
.map(|x| u32::from_be_bytes(x.try_into().unwrap()));
for reg in &mut self.r {
*reg = regs.next().ok_or(())?;
}
let mut regs = bytes[0x80..0x180]
.chunks_exact(8)
.map(|x| f64::from_be_bytes(x.try_into().unwrap()));
for reg in &mut self.f {
*reg = regs.next().ok_or(())?;
}
macro_rules! parse_regs {
($start:literal..$end:literal, $($reg:ident),*) => {
let mut regs = bytes[$start..$end]
.chunks_exact(4)
.map(|x| u32::from_be_bytes(x.try_into().unwrap()));
$(
self.$reg = regs.next().ok_or(())?;
)*
}
}
parse_regs!(0x180..0x19c, pc, msr, cr, lr, ctr, xer, fpscr);
let mut regs = bytes[0x19c..0x39c]
.chunks_exact(0x10)
.map(|x| u128::from_be_bytes(x.try_into().unwrap()));
for reg in &mut self.vr {
*reg = regs.next().ok_or(())?;
}
parse_regs!(0x39c..0x3a4, vscr, vrsave);
Ok(())
}
}
#[cfg(test)]
mod tests {
use super::*;
#[test]
fn ppc_core_round_trip() {
let regs_before = PowerPcCommonRegs {
r: [1; 32],
pc: 2,
msr: 3,
cr: 4,
lr: 5,
ctr: 6,
xer: 7,
fpscr: 8,
f: [9.0; 32],
vr: [52; 32],
vrsave: 10,
vscr: 11,
};
let mut data = vec![];
regs_before.gdb_serialize(|x| {
data.push(x.unwrap_or(b'x'));
});
assert_eq!(data.len(), 0x3a4);
let mut regs_after = PowerPcCommonRegs::default();
regs_after.gdb_deserialize(&data).unwrap();
assert_eq!(regs_before, regs_after);
}
}