{"payload":{"header_redesign_enabled":false,"results":[{"id":"167140400","archived":false,"color":"#3572A5","followers":962,"has_funding_file":false,"hl_name":"chipsalliance/riscv-dv","hl_trunc_description":"Random instruction generator for RISC-V processor verification","language":"Python","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":167140400,"name":"riscv-dv","owner_id":46612642,"owner_login":"chipsalliance","updated_at":"2024-05-29T02:34:53.567Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":61,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Achipsalliance%252Friscv-dv%2B%2Blanguage%253APython","metadata":null,"csrf_tokens":{"/chipsalliance/riscv-dv/star":{"post":"HmtI5f7vCQxXLfzYjDhjrDkylSLoV-TlQctl2wQLOeOodaNzC-QDZQCQ2EHbKZ6OMn25fY5nAliwBN_TGNCuuQ"},"/chipsalliance/riscv-dv/unstar":{"post":"MBj4zFeXZCJumEdr2RENw7UfRAwxW_0e3k8qY790r2Fr9TerwPPJAWBNADwORUH5DDFQVjRSTBen5WqhZO9MBA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"cJa0kWV_VJDmtSYz22gdZlVnAaSQmNjvpb628c2dzd7CHoSRIJ1XpL1VZagivP8lGcxcUgO6AfySK5ZYUGjRoQ"}}},"title":"Repository search results"}