Returning the signal name map when generating Verilog code

[xThaid]

Let's say I want to simulate a circuit in Verilator (or any other simulator requiring Verilog code) and I want to read values of a few debug signals in that simulation. For that I need to know what is the exact name in the generated Verilog code of a specific Amaranth Signal object.
How do I retrieve this mapping?

Apparently it is already computed in verilog.convert function, but not returned from the function. That variable is actually unused. Is there a specific reason that it is done that way?

[whitequark]

Backwards compatibility (the interface of verilog.convert originally did not include any provision for mapping signal names). For the time being, use verilog.convert_fragment function, which requires the inconvenience of you having to run Fragment.get yourself first.