{"payload":{"header_redesign_enabled":false,"results":[{"id":"115837888","archived":false,"color":"#b2b7f8","followers":121,"has_funding_file":false,"hl_name":"TimRudy/ice-chips-verilog","hl_trunc_description":"IceChips is a library of all common discrete logic devices in Verilog","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":115837888,"name":"ice-chips-verilog","owner_id":3942818,"owner_login":"TimRudy","updated_at":"2024-02-20T03:06:32.944Z","has_issues":true}},"sponsorable":false,"topics":["fpga","open-hardware","eda","digital-logic","icestorm","iverilog","logic-circuit","verilog-components","7400"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":79,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253ATimRudy%252Fice-chips-verilog%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/TimRudy/ice-chips-verilog/star":{"post":"9yI1daaQ2SfqdRh6RxWoFS9C6ep8gQcU-2CrpkaMnYH-DkAp40Vl8Y8KYVIssdGqmMEb3uf5_ei88STQydmQfA"},"/TimRudy/ice-chips-verilog/unstar":{"post":"qvPsAcuoOyNeCmeA6iDshXLz2nJ6FgmH_ko1cH1cOeeGYEqQVX7Ven6qWnmMPiGBrI7IEhgZtwwxcZBuz9j7lA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"AD-V-SaJvaj__pvKMXw8gJHPCObDxR92iUz77DO8JrG9s5RQPmKN1kaKSpk8lY8Z8oWfXHIWb31L204aaJWlOg"}}},"title":"Repository search results"}